ZHCSCX3C April 2014 – November 2014 CSD95379Q3M
PRODUCTION DATA.
6 Specifications
6.1 Absolute Maximum Ratings(1)
TA = 25°C (unless otherwise noted)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VIN to PGND | –0.3 | 20 | V | |
| VSW to PGND , VIN to VSW | –0.3 | 20 | V | |
| VSW to PGND, VIN to VSW (<10 ns) | –7 | 23 | V | |
| VDD to PGND | –0.3 | 6 | V | |
| PWM, SKIP# to PGND | –0.3 | 6 | V | |
| BOOT to PGND | –0.3 | 25 | V | |
| BOOT to PGND (<10 ns) | –2 | 28 | V | |
| BOOT to BOOT_R | –0.3 | 6 | V | |
| Power Dissipation, PD | 6 | W | ||
| Operating Temperature Range, TJ | –40 | 150 | °C | |
(1) Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| Tstg | Storage temperature range | –55 | 150 | °C | |
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) | –2000 | 2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | –500 | 500 | V | ||
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TA = 25° (unless otherwise noted)| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| VDD | Gate Drive Voltage | 4.5 | 5.5 | V | |
| VIN | Input Supply Voltage(1) | 16 | V | ||
| IOUT | Continuous Output Current | VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, ƒSW = 500 kHz, LOUT = 0.29 µH(2) |
20 | A | |
| IOUT-PK | Peak Output Current(3) | 45 | A | ||
| ƒSW | Switching Frequency | CBST = 0.1 µF (min) | 2000 | kHz | |
| On Time Duty Cycle | 85% | ||||
| Minimum PWM On Time | 40 | ns | |||
| Operating Temperature | –40 | 125 | °C | ||
(1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
(2) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(3) System conditions as defined in Note 1. Peak Output Current is applied for tp = 10 ms, duty cycle ≤1%
6.4 Thermal Information
TA = 25°C (unless otherwise noted)| THERMAL METRIC | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|
| RθJC(top) | Junction-to-Case Thermal Resistance (Top of package)(1) | 22.8 | °C/W | ||
| RθJB | Junction-to-Board Thermal Resistance(2) | 2.5 | |||
(1) RθJC(top) is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz (.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches,
0.06 inch (1.52 mm) thick FR4 board.
0.06 inch (1.52 mm) thick FR4 board.
(2) RθJB value based on hottest board temperature within 1 mm of the package.
6.5 Electrical Characteristics
TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| PLOSS | |||||
| Power Loss(1) | VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A, ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 25°C |
1.8 | W | ||
| Power Loss(2) | VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 12 A, ƒSW = 500 kHz, LOUT = 0.29 µH , TJ = 125°C |
2.3 | W | ||
| VIN | |||||
| VIN Quiescent Current, IQ | PWM = Float, VIN = 14.5 V, VDD = 5 V | 1 | µA | ||
| VDD | |||||
| Standby Supply Current, IDD | PWM = Float, VSKIP# = VDD or 0 V | 130 | µA | ||
| VSKIP# = Float | 8 | µA | |||
| Operating Supply Current, IDD | PWM = 50% Duty cycle, ƒSW = 500 kHz | 5.5 | mA | ||
| POWER-ON RESET AND UNDERVOLTAGE LOCKOUT | |||||
| Power-On Reset, VDD Rising | 4.15 | V | |||
| UVLO, VDD Falling | 3.7 | V | |||
| Hysteresis | 0.2 | mV | |||
| PWM AND SKIP# I/O SPECIFICATIONS | |||||
| Input Impedance, RI | Pull up to VDD | 1700 | kΩ | ||
| Pull Down to GND | 800 | kΩ | |||
| Logic Level High, VIH | 2.65 | V | |||
| Logic Level Low, VIL | 0.6 | V | |||
| Hysteresis, VIH | 0.2 | V | |||
| Tri-State Voltage, VTS | 1.3 | 2 | V | ||
| Tri-State Activation (Falling) PWM, Time, tHOLD(off1)(2) | 60 | ns | |||
| Tri-State Activation (Rising) PWM, Time, tHOLD(off2)(2) | 60 | ns | |||
| Tri-State Activation (Falling) SKIP#, Time, tTSKF(2) | 1 | ns | |||
| Tri-State Activation (Rising) SKIP#, Time, tTSKR(2) | 1 | ns | |||
| Tri-State Exit Time PWM, t3RD(PWM)(2) | 100 | ns | |||
| Tri-State Exit Time SKIP#, t3RD(SKIP#)(2) | 50 | us | |||
| BOOTSTRAP SWITCH | |||||
| Forward Voltage, VFBOOT | Measured from VDD to VBOOT, IF = 20 mA | 120 | 240 | mV | |
| Reverse Leakage, IRBOOT(1) | VBOOT – VDD = 25 V | 2 | µA | ||
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
(2) Specified by design
6.6 Typical Characteristics
TJ = 125°C, unless stated otherwise. The Typical CSD95379Q3M System Characteristic curves are based on measurements made on a PCB design with dimensions of 4 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1 oz. copper thickness. See the Application and Implementation section for detailed explanation.
