ZHCSGV7F July 2017 – January 2024 CDCI6214
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The EEPROM is split into a common base page which holds common settings. Then there are two pages for customized settings. Page 0 is selected using EEPROMSEL = Low. Page 1 is selected using EEPROMSEL = High.
The CRC value is stored at the end of page 1 in word 0x3F.
| WORD NO. | SECTION | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 0h | Base | cp_dly[0] | cal_mute | shift_left[1] | shift_left[0] | gpio3_gf_en | gpio2_gf_en | acal_en | pdn_pll_vcobuf2 | pdn_pll_vco | pdn_pll_vcobuf | pdn_pll_cp | pdn_pll_lockdet | pdn_pll_pfd | pdn_pll_psfb | regcommit_page | resetn_soft |
| 1h | Base | ac_cmp_dly[0] | pll_lock_dly[4] | pll_lock_dly[3] | pll_lock_dly[2] | pll_lock_dly[1] | pll_lock_dly[0] | ac_init_dly[5] | ac_init_dly[4] | ac_init_dly[3] | ac_init_dly[2] | ac_init_dly[1] | ac_init_dly[0] | cp_dly[4] | cp_dly[3] | cp_dly[2] | cp_dly[1] |
| 2h | Base | 0 | 0 | 0 | 0 | 0 | 0 | err_cnt[2] | err_cnt[1] | err_cnt[0] | fc_setl_dly[1] | fc_setl_dly[0] | ac_cmp_dly[5] | ac_cmp_dly[4] | ac_cmp_dly[3] | ac_cmp_dly[2] | ac_cmp_dly[1] |
| 3h | Base | pll_pfd_dly_ctrl[1] | pll_pfd_dly_ctrl[0] | pll_lockdet_window[2] | pll_lockdet_window[1] | pll_lockdet_window[0] | pll_lockdet_wait[1] | pll_lockdet_wait[0] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 4h | Base | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 5h | Base | chx_diffbuf_ibias_trim[1] | chx_diffbuf_ibias_trim[0] | chx_lvcmos_drv | chx_en_cmosslow | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 6h | Base | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | chx_lvds_cmtrim_inc[1] | chx_lvds_cmtrim_inc[0] | chx_lvds_cmtrim_dec[1] | chx_lvds_cmtrim_dec[0] | chx_diffbuf_ibias_trim[3] | chx_diffbuf_ibias_trim[2] |
| 7h | Base | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 8h | Base | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |
| 9h | Base | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 |
| Ah | Base | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 |
| Bh | Base | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| WORD NO. | SECTION | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Ch | Page 0 | gpio4_input_sel[3] | gpio4_input_sel[2] | gpio4_input_sel[1] | gpio4_input_sel[0] | gpio1_input_sel[3] | gpio1_input_sel[2] | gpio1_input_sel[1] | gpio1_input_sel[0] | i2c_a0 | gpio0_input_sel | gpio4_dir_sel | gpio1_dir_sel | gpio0_dir_sel | zdm_clocksel | zdm_mode | mode |
| Dh | Page 0 | gpio4_output_sel[3] | gpio4_output_sel[2] | gpio4_output_sel[1] | gpio4_output_sel[0] | gpio1_output_sel[3] | gpio1_output_sel[2] | gpio1_output_sel[1] | gpio1_output_sel[0] | 0 | 1 | 1 | 0 | 1 | 0 | ref_mux_src | ref_mux |
| Eh | Page 0 | 1 | pdn_ch4 | 1 | pdn_ch3 | 1 | pdn_ch2 | 1 | pdn_ch1 | 1 | 0 | rsrvd_1[1] | rsrvd_1[0] | gpio0_output_sel[3] | gpio0_output_sel[2] | gpio0_output_sel[1] | gpio0_output_sel[0] |
| Fh | Page 0 | ip_xo_cload[2] | ip_xo_cload[1] | ip_xo_cload[0] | 0 | 0 | ip_xo_gm[3] | ip_xo_gm[2] | ip_xo_gm[1] | ip_xo_gm[0] | xin_inbuf_ctrl[1] | xin_inbuf_ctrl[0] | zdm_auto | bypass_cal | bypass_config | pdn_pll_psb | pdn_pll_psa |
| 10h | Page 0 | ip_byp_en_ch3 | ip_byp_en_ch2 | ip_byp_en_ch1 | ip_byp_en_y0 | ip_byp_mux | ip_rdiv[7] | ip_rdiv[6] | ip_rdiv[5] | ip_rdiv[4] | ip_rdiv[3] | ip_rdiv[2] | ip_rdiv[1] | ip_rdiv[0] | ref_inbuf_ctrl | ip_xo_cload[4] | ip_xo_cload[3] |
| 11h | Page 0 | pll_ndiv[13] | pll_ndiv[12] | pll_ndiv[11] | pll_ndiv[10] | pll_ndiv[9] | pll_ndiv[8] | pll_ndiv[7] | pll_ndiv[6] | pll_ndiv[5] | pll_ndiv[4] | pll_ndiv[3] | pll_ndiv[2] | pll_ndiv[1] | pll_ndiv[0] | 0 | ip_byp_en_ch4 |
| 12h | Page 0 | pll_cp_up[3] | pll_cp_up[2] | pll_cp_up[1] | pll_cp_up[0] | pll_cp_dn[5] | pll_cp_dn[4] | pll_cp_dn[3] | pll_cp_dn[2] | pll_cp_dn[1] | pll_cp_dn[0] | pll_psb[1] | pll_psb[0] | pll_psa[1] | pll_psa[0] | pll_psfb[1] | pll_psfb[0] |
| 13h | Page 0 | pll_lf_zcap[4] | pll_lf_zcap[3] | pll_lf_zcap[2] | pll_lf_zcap[1] | pll_lf_zcap[0] | pll_lf_res[3] | pll_lf_res[2] | pll_lf_res[1] | pll_lf_res[0] | pll_lf_pcap[4] | pll_lf_pcap[3] | pll_lf_pcap[2] | pll_lf_pcap[1] | pll_lf_pcap[0] | pll_cp_up[5] | pll_cp_up[4] |
| 14h | Page 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 15h | Page 0 | ch1_iod_div[6] | ch1_iod_div[5] | ch1_iod_div[4] | ch1_iod_div[3] | ch1_iod_div[2] | ch1_iod_div[1] | ch1_iod_div[0] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 16h | Page 0 | 0 | 0 | ch1_outbuf_ctrl[2] | ch1_outbuf_ctrl[1] | ch1_outbuf_ctrl[0] | ch1_mux[1] | ch1_mux[0] | ch1_iod_mux[1] | ch1_iod_mux[0] | ch1_iod_div[13] | ch1_iod_div[12] | ch1_iod_div[11] | ch1_iod_div[10] | ch1_iod_div[9] | ch1_iod_div[8] | ch1_iod_div[7] |
| 17h | Page 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | ch1_glitchless_en | ch1_sync_delay[4] | ch1_sync_delay[3] | ch1_sync_delay[2] | ch1_sync_delay[1] | ch1_sync_delay[0] | ch1_sync_en | ch1_mute_sel | ch1_mute |
| 18h | Page 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ch1_1p8vdet | 0 |
| 19h | Page 0 | ch2_iod_div[4] | ch2_iod_div[3] | ch2_iod_div[2] | ch2_iod_div[1] | ch2_iod_div[0] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 1Ah | Page 0 | ch2_outbuf_ctrl[2] | ch2_outbuf_ctrl[1] | ch2_outbuf_ctrl[0] | ch2_mux[1] | ch2_mux[0] | ch2_iod_mux[1] | ch2_iod_mux[0] | ch2_iod_div[13] | ch2_iod_div[12] | ch2_iod_div[11] | ch2_iod_div[10] | ch2_iod_div[9] | ch2_iod_div[8] | ch2_iod_div[7] | ch2_iod_div[6] | ch2_iod_div[5] |
| 1Bh | Page 0 | 1 | 0 | 1 | 0 | 0 | ch2_glitchless_en | ch2_sync_delay[4] | ch2_sync_delay[3] | ch2_sync_delay[2] | ch2_sync_delay[1] | ch2_sync_delay[0] | ch2_sync_en | ch2_mute_sel | ch2_mute | ch2_cmos_pol[1] | ch2_cmos_pol[0] |
| 1Ch | Page 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ch2_1p8vdet | 0 | 0 | 0 |
| 1Dh | Page 0 | ch3_iod_div[2] | ch3_iod_div[1] | ch3_iod_div[0] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 1Eh | Page 0 | ch3_outbuf_ctrl[0] | ch3_mux[1] | ch3_mux[0] | ch3_iod_mux[1] | ch3_iod_mux[0] | ch3_iod_div[13] | ch3_iod_div[12] | ch3_iod_div[11] | ch3_iod_div[10] | ch3_iod_div[9] | ch3_iod_div[8] | ch3_iod_div[7] | ch3_iod_div[6] | ch3_iod_div[5] | ch3_iod_div[4] | ch3_iod_div[3] |
| 1Fh | Page 0 | 0 | 0 | 0 | ch3_glitchless_en | ch3_sync_delay[4] | ch3_sync_delay[3] | ch3_sync_delay[2] | ch3_sync_delay[1] | ch3_sync_delay[0] | ch3_sync_en | ch3_mute_sel | ch3_mute | ch3_cmos_pol[1] | ch3_cmos_pol[0] | ch3_outbuf_ctrl[2] | ch3_outbuf_ctrl[1] |
| 20h | Page 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ch3_1p8vdet | 1 | 0 | 0 | 1 | 0 |
| 21h | Page 0 | ch4_iod_div[0] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 22h | Page 0 | ch4_mux[0] | ch4_iod_mux[1] | ch4_iod_mux[0] | ch4_iod_div[13] | ch4_iod_div[12] | ch4_iod_div[11] | ch4_iod_div[10] | ch4_iod_div[9] | ch4_iod_div[8] | ch4_iod_div[7] | ch4_iod_div[6] | ch4_iod_div[5] | ch4_iod_div[4] | ch4_iod_div[3] | ch4_iod_div[2] | ch4_iod_div[1] |
| 23h | Page 0 | 0 | ch4_glitchless_en | ch4_sync_delay[4] | ch4_sync_delay[3] | ch4_sync_delay[2] | ch4_sync_delay[1] | ch4_sync_delay[0] | ch4_sync_en | ch4_mute_sel | ch4_mute | 0 | 0 | ch4_outbuf_ctrl[2] | ch4_outbuf_ctrl[1] | ch4_outbuf_ctrl[0] | ch4_mux[1] |
| 24h | Page 0 | 0 | 0 | 1 | 1 | pll_en_cp | ch0_lvcmos_drv[1] | ch0_lvcmos_drv[0] | 1 | ch4_1p8vdet | 1 | 0 | 0 | 1 | 0 | 1 | 0 |
| 25h | Page 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| WORD NO. | SECTION | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 26h | Page 1 | gpio4_input_sel[3] | gpio4_input_sel[2] | gpio4_input_sel[1] | gpio4_input_sel[0] | gpio1_input_sel[3] | gpio1_input_sel[2] | gpio1_input_sel[1] | gpio1_input_sel[0] | i2c_a0 | gpio0_input_sel | gpio4_dir_sel | gpio1_dir_sel | gpio0_dir_sel | zdm_clocksel | zdm_mode | mode |
| 27h | Page 1 | gpio4_output_sel[3] | gpio4_output_sel[2] | gpio4_output_sel[1] | gpio4_output_sel[0] | gpio1_output_sel[3] | gpio1_output_sel[2] | gpio1_output_sel[1] | gpio1_output_sel[0] | 0 | 1 | 1 | 0 | 1 | 0 | ref_mux_src | ref_mux |
| 28h | Page 1 | 1 | pdn_ch4 | 1 | pdn_ch3 | 1 | pdn_ch2 | 1 | pdn_ch1 | 1 | 0 | rsrvd_1[1] | rsrvd_1[0] | gpio0_output_sel[3] | gpio0_output_sel[2] | gpio0_output_sel[1] | gpio0_output_sel[0] |
| 29h | Page 1 | ip_xo_cload[2] | ip_xo_cload[1] | ip_xo_cload[0] | 0 | 0 | ip_xo_gm[3] | ip_xo_gm[2] | ip_xo_gm[1] | ip_xo_gm[0] | xin_inbuf_ctrl[1] | xin_inbuf_ctrl[0] | zdm_auto | bypass_cal | bypass_config | pdn_pll_psb | pdn_pll_psa |
| 2Ah | Page 1 | ip_byp_en_ch3 | ip_byp_en_ch2 | ip_byp_en_ch1 | ip_byp_en_y0 | ip_byp_mux | ip_rdiv[7] | ip_rdiv[6] | ip_rdiv[5] | ip_rdiv[4] | ip_rdiv[3] | ip_rdiv[2] | ip_rdiv[1] | ip_rdiv[0] | ref_inbuf_ctrl | ip_xo_cload[4] | ip_xo_cload[3] |
| 2Bh | Page 1 | pll_ndiv[13] | pll_ndiv[12] | pll_ndiv[11] | pll_ndiv[10] | pll_ndiv[9] | pll_ndiv[8] | pll_ndiv[7] | pll_ndiv[6] | pll_ndiv[5] | pll_ndiv[4] | pll_ndiv[3] | pll_ndiv[2] | pll_ndiv[1] | pll_ndiv[0] | 0 | ip_byp_en_ch4 |
| 2Ch | Page 1 | pll_cp_up[3] | pll_cp_up[2] | pll_cp_up[1] | pll_cp_up[0] | pll_cp_dn[5] | pll_cp_dn[4] | pll_cp_dn[3] | pll_cp_dn[2] | pll_cp_dn[1] | pll_cp_dn[0] | pll_psb[1] | pll_psb[0] | pll_psa[1] | pll_psa[0] | pll_psfb[1] | pll_psfb[0] |
| 2Dh | Page 1 | pll_lf_zcap[4] | pll_lf_zcap[3] | pll_lf_zcap[2] | pll_lf_zcap[1] | pll_lf_zcap[0] | pll_lf_res[3] | pll_lf_res[2] | pll_lf_res[1] | pll_lf_res[0] | pll_lf_pcap[4] | pll_lf_pcap[3] | pll_lf_pcap[2] | pll_lf_pcap[1] | pll_lf_pcap[0] | pll_cp_up[5] | pll_cp_up[4] |
| 2Eh | Page 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 2Fh | Page 1 | ch1_iod_div[6] | ch1_iod_div[5] | ch1_iod_div[4] | ch1_iod_div[3] | ch1_iod_div[2] | ch1_iod_div[1] | ch1_iod_div[0] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 30h | Page 1 | 0 | 0 | ch1_outbuf_ctrl[2] | ch1_outbuf_ctrl[1] | ch1_outbuf_ctrl[0] | ch1_mux[1] | ch1_mux[0] | ch1_iod_mux[1] | ch1_iod_mux[0] | ch1_iod_div[13] | ch1_iod_div[12] | ch1_iod_div[11] | ch1_iod_div[10] | ch1_iod_div[9] | ch1_iod_div[8] | ch1_iod_div[7] |
| 31h | Page 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | ch1_glitchless_en | ch1_sync_delay[4] | ch1_sync_delay[3] | ch1_sync_delay[2] | ch1_sync_delay[1] | ch1_sync_delay[0] | ch1_sync_en | ch1_mute_sel | ch1_mute |
| 32h | Page 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ch1_1p8vdet | 0 |
| 33h | Page 1 | ch2_iod_div[4] | ch2_iod_div[3] | ch2_iod_div[2] | ch2_iod_div[1] | ch2_iod_div[0] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
| 34h | Page 1 | ch2_outbuf_ctrl[2] | ch2_outbuf_ctrl[1] | ch2_outbuf_ctrl[0] | ch2_mux[1] | ch2_mux[0] | ch2_iod_mux[1] | ch2_iod_mux[0] | ch2_iod_div[13] | ch2_iod_div[12] | ch2_iod_div[11] | ch2_iod_div[10] | ch2_iod_div[9] | ch2_iod_div[8] | ch2_iod_div[7] | ch2_iod_div[6] | ch2_iod_div[5] |
| 35h | Page 1 | 1 | 0 | 1 | 0 | 0 | ch2_glitchless_en | ch2_sync_delay[4] | ch2_sync_delay[3] | ch2_sync_delay[2] | ch2_sync_delay[1] | ch2_sync_delay[0] | ch2_sync_en | ch2_mute_sel | ch2_mute | ch2_cmos_pol[1] | ch2_cmos_pol[0] |
| 36h | Page 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ch2_1p8vdet | 0 | 0 | 0 |
| 37h | Page 1 | ch3_iod_div[2] | ch3_iod_div[1] | ch3_iod_div[0] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
| 38h | Page 1 | ch3_outbuf_ctrl[0] | ch3_mux[1] | ch3_mux[0] | ch3_iod_mux[1] | ch3_iod_mux[0] | ch3_iod_div[13] | ch3_iod_div[12] | ch3_iod_div[11] | ch3_iod_div[10] | ch3_iod_div[9] | ch3_iod_div[8] | ch3_iod_div[7] | ch3_iod_div[6] | ch3_iod_div[5] | ch3_iod_div[4] | ch3_iod_div[3] |
| 39h | Page 1 | 0 | 0 | 0 | ch3_glitchless_en | ch3_sync_delay[4] | ch3_sync_delay[3] | ch3_sync_delay[2] | ch3_sync_delay[1] | ch3_sync_delay[0] | ch3_sync_en | ch3_mute_sel | ch3_mute | ch3_cmos_pol[1] | ch3_cmos_pol[0] | ch3_outbuf_ctrl[2] | ch3_outbuf_ctrl[1] |
| 3Ah | Page 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ch3_1p8vdet | 1 | 0 | 0 | 1 | 1 |
| 3Bh | Page 1 | ch4_iod_div[0] | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 |
| 3Ch | Page 1 | ch4_mux[0] | ch4_iod_mux[1] | ch4_iod_mux[0] | ch4_iod_div[13] | ch4_iod_div[12] | ch4_iod_div[11] | ch4_iod_div[10] | ch4_iod_div[9] | ch4_iod_div[8] | ch4_iod_div[7] | ch4_iod_div[6] | ch4_iod_div[5] | ch4_iod_div[4] | ch4_iod_div[3] | ch4_iod_div[2] | ch4_iod_div[1] |
| 3Dh | Page 1 | 0 | ch4_glitchless_en | ch4_sync_delay[4] | ch4_sync_delay[3] | ch4_sync_delay[2] | ch4_sync_delay[1] | ch4_sync_delay[0] | ch4_sync_en | ch4_mute_sel | ch4_mute | 0 | 0 | ch4_outbuf_ctrl[2] | ch4_outbuf_ctrl[1] | ch4_outbuf_ctrl[0] | ch4_mux[1] |
| 3Eh | Page 1 | 0 | 0 | 1 | 1 | pll_en_cp | ch0_lvcmos_drv[1] | ch0_lvcmos_drv[0] | 1 | ch4_1p8vdet | 1 | 0 | 0 | 1 | 0 | 1 | 0 |
| 3Fh | Page 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 |