ZHCSGV7F July 2017 – January 2024 CDCI6214
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Device Comparison
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 EEPROM Characteristics
- 6.6 Reference Input, Single-Ended and Differential Mode Characteristics (REFP, REFN, FB_P, FB_N)
- 6.7 Reference Input, Crystal Mode Characteristics (XIN, XOUT)
- 6.8 General-Purpose Input and Output Characteristics (GPIO[4:1], SYNC/RESETN)
- 6.9 Triple Level Input Characteristics (EEPROMSEL, REFSEL)
- 6.10 Reference Mux Characteristics
- 6.11 Phase-Locked Loop Characteristics
- 6.12 Closed-Loop Output Jitter Characteristics
- 6.13 Output Mux Characteristics
- 6.14 LVCMOS Output Characteristics
- 6.15 HCSL Output Characteristics
- 6.16 LVDS DC-Coupled Output Characteristics
- 6.17 Programmable Differential AC-Coupled Output Characteristics
- 6.18 Output Skew and Delay Characteristics
- 6.19 Output Synchronization Characteristics
- 6.20 Timing Characteristics
- 6.21 I2C-Compatible Serial Interface Characteristics (SDA/GPIO2, SCL/GPIO3)
- 6.22 Timing Requirements, I2C-Compatible Serial Interface (SDA/GPIO2, SCL/GPIO3)
- 6.23 Power Supply Characteristics
- 6.24 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 9 Application and Implementation
- 10Register Maps
- 11Device and Documentation Support
- 12Revision History
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGE|24
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
7.1.2 Outputs
Figure 7-3 LVCMOS Output
Figure 7-4 LVDS Output, DC-Coupled
Figure 7-5 LVDS Output AC-Coupled
Figure 7-6 Differential AC-Coupled (CML, LVPECL)
Figure 7-7 Differential Output Voltage and Rise/Fall Time
A. Differential waveform created using math function in scope subtracting positive from negative output pin waveform: YxP - YxN.
B. Slew rate measured using absolute ± 150 mV on the differential waveform. This correlates to the cross-point of the single ended positive and negative waveform.
Figure 7-8 HCSL, Differential Rise and Fall Time
Figure 7-9 HCSL, Slew Rate Variation
A. Measurement conducted using the single ended waveforms. Total variation of the crossing point of rising YxP and falling YxN edges.
Figure 7-10 HCSL, Delta Crossing Voltage
Figure 7-11 HCSL, Phase Noise Measurement
A. Measured using Tektronix DPO75902SX oscilloscope. Recommended to use an oscilloscope bandwidth setting of 4/8 GHz and vertical setting of 50mV/division. Data processed using Clock Jitter Tool: Ver:1.6.7.2.
Figure 7-12 HCSL PCIe Test Load Setup