ZHCSPO2 September 2023 ADC32RF52
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| ADC TIMING SPECIFICATIONS | ||||||
| TAD | Aperture Delay | 0.17 | ns | |||
| Aperure Delay variation | 0.07 | ns | ||||
| TA | Aperture Jitter | 50 | fs | |||
| Overload recovery time | 3-dB overload condition | 10 | clock cycles | |||
| 6-dB overload condition | 50 | |||||
| tADC | ADC latency from sampling instant to internal hand-off to digital | 68 | clock cycles | |||
| Internal propagation delay | 5 | ns | ||||
| Latency adder for 2x or 4x averaging | 4 | clock cycles | ||||
| Deterministic delay from digital block (DDC (if used) and JESD interface) | LMFS = 8-2-8-20 | 260 | clock cycles | |||
| LMFS = 8-2-2-4 | 280 | |||||
| 4x complex decimation, LMFS = 8-4-2-2 | 456 | |||||
| 4x real decimation, LMFS = 4-2-2-2 | 456 | |||||
| 4x decimation, F (number of octets) = 2 | 394 | |||||
| 4x decimation, F = 4 | 374 | |||||
| 4x decimation, F = 8 | 367 | |||||
| 8x decimation, F = 2 | 560 | |||||
| 8x decimation, F = 4 | 520 | |||||
| 8x decimation, F = 8 | 506 | |||||
| 8x decimation, F = 16 | 491 | |||||
| 16x decimation, F = 2 | 900 | |||||
| 16x decimation, F = 4 | 820 | |||||
| 16x decimation, F = 8 | 792 | |||||
| 16x decimation, F = 16 | 762 | |||||
| 16x decimation, F = 32 | 748 | |||||
| 32x decimation, F = 2 | 1596 | |||||
| 32x decimation, F = 4 | 1436 | |||||
| 32x decimation, F = 8 | 1380 | |||||
| 32x decimation, F = 16 | 1320 | |||||
| 32x decimation, F = 32 | 1292 | |||||
| 64x decimation, F = 2 | 2940 | |||||
| 64x decimation, F = 4 | 2620 | |||||
| 64x decimation, F = 8 | 2508 | |||||
| 64x decimation, F = 16 | 2388 | |||||
| 64x decimation, F = 32 | 2332 | |||||
| 128x decimation, F = 2 | 5668 | |||||
| 128x decimation, F = 4 | 5028 | |||||
| 128x decimation, F = 8 | 4804 | |||||
| 128x decimation, F = 16 | 4564 | |||||
| 128x decimation, F = 32 | 4452 | |||||
| SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input | ||||||
| fCLK(SCLK) | Serial clock frequency | 1 | 20 | MHz | ||
| tSU(SEN) | SEN to rising edge of SCLK | 10 | ns | |||
| tH(SEN) | SEN from rising edge of SCLK | 10 | ns | |||
| tSU(SDIO) | SDIO to rising edge of SCLK | 10 | ns | |||
| tH(SDIO) | SDIO from rising edge of SCLK | 10 | ns | |||
| SERIAL PROGRAMMING INTERFACE (SDIO) - Output | ||||||
| t(OZD) | SDIO tri-state to driven | 10 | ns | |||
| t(ODZ) | SDIO data to tri-state | 14 | ns | |||
| t(OD) | SDIO valid from falling edge of SCLK | 10 | ns | |||
| TIMING: SYSREFP/M | ||||||
| ts(SYSREF) | Setup time, SYSREFP/M valid to rising edge of CLKP/M | 50 | ps | |||
| th(SYSREF) | Hold time, SYSREFP/M valid to rising edge of CLKP/M | 50 | ps | |||
| CML SERDES OUTPUTS: DA[0:3]P/M, DB[0:3]P/M | ||||||
| fSerdes | Serdes bit rate | 0.5 | 12.8 | 13.0 | Gbps | |
| RJ | Random jitter, RMS | RPAT, 6.4 Gbps | 0.7 | ps | ||
| RPAT, 12.8 Gbps | 0.6 | |||||
| DJ | Deterministic jitter, peak to peak | RPAT, 6.4 Gbps | 8.9 | ps | ||
| RPAT, 12.8 Gbps | 14.7 | |||||
| TJ | Total jitter, peak to peak | RPAT, 6.4 Gbps | 19.5 | ps | ||
| RPAT, 12.8 Gbps | 24 | |||||