ZHCSHX9L November 2008 – February 2019 ADC14155QML-SP
PRODUCTION DATA.
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Single-ended versus differential clock mode and output data format are selectable using this quad-state function pin. Table 4 shows how to select between the clock modes and the output data formats.
| CLK_SEL/DF Input Voltage | Clock Mode | Output Data Format |
|---|---|---|
| VA | Differential | 2's Complement |
| (2 / 3) * VA | Differential | Offset Binary |
| (1 / 3) * VA | Single-Ended | 2's Complement |
| AGND | Single-Ended | Offset Binary |