SN74ALVCH162827

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具有總線保持和三態(tài)輸出的 20 通道、1.65V 至 3.6V 緩沖器

產(chǎn)品詳情

Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 20 IOL (max) (mA) 12 Supply current (max) (μA) 40 IOH (max) (mA) -12 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 20 IOL (max) (mA) 12 Supply current (max) (μA) 40 IOH (max) (mA) -12 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Damping resistors, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm2 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm2 14 x 8.1 TVSOP (DGV) 56 72.32 mm2 11.3 x 6.4
  • Member of the Texas Instruments Widebus? Family
  • Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments Incorporated.
  • Member of the Texas Instruments Widebus? Family
  • Output Ports Have Equivalent 26- Series Resistors, So No External Resistors Are Required
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Widebus is a trademark of Texas Instruments Incorporated.

This 20-bit noninverting buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH162827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

This 20-bit noninverting buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH162827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 SN74ALVCH162827 數(shù)據(jù)表 (Rev. H) 2004年 8月 16日
應(yīng)用手冊 Drive Transmission Lines With Logic PDF | HTML 2020年 10月 20日
應(yīng)用手冊 An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018年 9月 17日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應(yīng)用手冊 Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
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用戶指南 ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002年 8月 1日
更多文獻(xiàn)資料 Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
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應(yīng)用手冊 Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
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仿真模型

SN74ALVCH162827 Behavioral SPICE Model

SCEM756.ZIP (7 KB) - PSpice Model
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仿真模型

SN74ALVCH162827 IBIS Model (Rev. B)

SCEM027B.ZIP (59 KB) - IBIS Model
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封裝 引腳 CAD 符號、封裝和 3D 模型
SSOP (DL) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian
TVSOP (DGV) 56 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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