SN74ALVCH16827

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具有總線保持和三態(tài)輸出的 20 通道、1.65V 至 3.6V 緩沖器

產(chǎn)品詳情

Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 20 IOL (max) (mA) 24 Supply current (max) (μA) 40 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ALVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 3.6 Number of channels 20 IOL (max) (mA) 24 Supply current (max) (μA) 40 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
SSOP (DL) 56 190.647 mm2 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm2 14 x 8.1
  • Member of the Texas Instruments Widebus? Family
  • EPIC? (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

Widebus, EPIC are trademarks of Texas Instruments.
  • Member of the Texas Instruments Widebus? Family
  • EPIC? (Enhanced-Performance Implanted CMOS) Submicron Process
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages

Widebus, EPIC are trademarks of Texas Instruments.

This 20-bit noninverting buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16827 is characterized for operation from -40°C to 85°C.

This 20-bit noninverting buffer/driver is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVCH16827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH16827 is characterized for operation from -40°C to 85°C.
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類型 標(biāo)題 下載最新的英語版本 日期
* 數(shù)據(jù)表 SN74ALVCH16827 數(shù)據(jù)表 (Rev. D) 2004年 9月 2日
應(yīng)用手冊(cè) An Overview of Bus-Hold Circuit and the Applications (Rev. B) 2018年 9月 17日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應(yīng)用手冊(cè) Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語版本 (Rev.AC) PDF | HTML 2014年 11月 17日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應(yīng)用手冊(cè) Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
應(yīng)用手冊(cè) TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
用戶指南 ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B) 2002年 8月 1日
更多文獻(xiàn)資料 Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
應(yīng)用手冊(cè) 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
應(yīng)用手冊(cè) Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 1999年 9月 8日
應(yīng)用手冊(cè) TI SN74ALVC16835 Component Specification Analysis for PC100 1998年 8月 3日
應(yīng)用手冊(cè) Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A) 1998年 5月 13日
應(yīng)用手冊(cè) Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
應(yīng)用手冊(cè) Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
應(yīng)用手冊(cè) CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
應(yīng)用手冊(cè) Timing Differences of 10-pF Versus 50pF Loading 1996年 11月 1日
應(yīng)用手冊(cè) Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
應(yīng)用手冊(cè) Live Insertion 1996年 10月 1日
應(yīng)用手冊(cè) Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

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仿真模型

HSPICE Model for SN74ALVCH16827

SCEJ250.ZIP (338 KB) - HSpice Model
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仿真模型

SN74ALVCH16827 Behavioral SPICE Model

SCEM752.ZIP (7 KB) - PSpice Model
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仿真模型

SN74ALVCH16827 IBIS Model (Rev. A)

SCEM163A.ZIP (58 KB) - IBIS Model
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封裝 引腳 CAD 符號(hào)、封裝和 3D 模型
SSOP (DL) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
包含信息：
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

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