SN54S74

正在供貨

具有預(yù)置端的雙通道下降沿觸發(fā)式 D 類觸發(fā)器

產(chǎn)品詳情

Number of channels 2 Technology family S Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 50 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (μA) 25000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
Number of channels 2 Technology family S Supply voltage (min) (V) 4.75 Supply voltage (max) (V) 5.25 Input type Bipolar Output type Push-Pull Clock frequency (max) (MHz) 50 IOL (max) (mA) 20 IOH (max) (mA) -1 Supply current (max) (μA) 25000 Features High speed (tpd 10-50ns) Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 14 130.4652 mm2 19.56 x 6.67 CFP (W) 14 58.023 mm2 9.21 x 6.3
  • Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 
  • Package Options Include Plastic “Small Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability

 

These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.

The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74' family is characterized for operation from 0°C to 70°C.

 

These devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the D input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs.

The SN54' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74' family is characterized for operation from 0°C to 70°C.

 
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類型 標(biāo)題 下載最新的英語(yǔ)版本 日期
* 數(shù)據(jù)表 Dual D-Type Positive-Edge -Triggered Flip-Flops With Preset And Clear 數(shù)據(jù)表 1988年 3月 1日

訂購(gòu)和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
包含信息：
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

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