SN54HC195

正在供貨

4 位并行訪問移位寄存器

產(chǎn)品詳情

Technology family HC Operating temperature range (°C) -55 to 125 Rating Military
Technology family HC Operating temperature range (°C) -55 to 125 Rating Military
CDIP (J) 16 135.3552 mm2 19.56 x 6.92
  • Synchronous Parallel Load
  • Positive-Edge-Triggered Clocking
  • J and K Inputs to First Stage
  • Complementary Outputs From Last Stage
  • Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers
  • Dependable Texas lnstruments Quality and Reliability
  • Synchronous Parallel Load
  • Positive-Edge-Triggered Clocking
  • J and K Inputs to First Stage
  • Complementary Outputs From Last Stage
  • Package Options: Plastic and Ceramic DIPS and Ceramic Chip Carriers
  • Dependable Texas lnstruments Quality and Reliability

These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD).

Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table.

The SN54HC195 is characterized for operation over the full military temperature range of –55°C to 125°C.

These 4-bit registers feature parallel inputs, parallel outputs, J-K serial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QA and QD).

Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.

Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table.

The SN54HC195 is characterized for operation over the full military temperature range of –55°C to 125°C.
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類型 標題 下載最新的英語版本 日期
* 數(shù)據(jù)表 4-Bit Parallel-Access Shift Registers 數(shù)據(jù)表 (Rev. A) 2007年 11月 16日

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包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

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