SN54ALS74A
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
These devices contain two independent positive-edge-triggered
D-type flip-flops. A low level at the preset (
) or clear (
) inputs sets or resets the outputs
regardless of the levels of the other inputs. When
and
are inactive (high), data at the
data (D) input meeting the setup-time requirements are transferred to
the outputs on the positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a voltage level and is not directly
related to the rise time of CLK. Following the hold-time interval,
data at the D input can be changed without affecting the levels at
the outputs.
The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.
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功能與比較器件相同,但引腳排列有所不同
技術文檔
| 類型 | 標題 | 下載最新的英語版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 數據表 | Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset 數據表 (Rev. C) | 1995年 8月 1日 |
訂購和質量
- RoHS
- REACH
- 器件標識
- 引腳鍍層/焊球材料
- MSL 等級/回流焊峰值溫度
- MTBF/時基故障估算
- 材料成分
- 鑒定摘要
- 持續(xù)可靠性監(jiān)測
- 制造廠地點
- 封裝廠地點