產(chǎn)品詳情

PGA/VGA PGA Number of channels 2 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (μV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 46 Architecture CMOS Features Binary gains, Daisy chain, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (μV√Hz) 0.012 Slew rate (typ) (V/μs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
PGA/VGA PGA Number of channels 2 Vs (min) (V) 2.2 Vs (max) (V) 5.5 Input type Single-ended Output type Single-ended Input offset drift (±) (typ) (μV/°C) 0.6 Interface type SPI Noise at 1 kHz (typ) (V√Hz) 0.000000013 BW at Acl (MHz) 10 Acl, min spec gain (V/V) 1 Gain (max) (dB) 46 Architecture CMOS Features Binary gains, Daisy chain, Shutdown Vos (offset voltage at 25°C) (typ) (mV) 0.025 Input voltage noise (typ) (μV√Hz) 0.012 Slew rate (typ) (V/μs) 3 Iq per channel (typ) (mA) 1.08 Gain error (typ) (%) 0.006 Gain drift (max) (ppm/°C) 0.5 Rating Catalog Operating temperature range (°C) -40 to 125
VSSOP (DGS) 10 14.7 mm2 3 x 4.9
  • Rail-to-Rail Input and Output
  • Offset: 25 μV (Typical), 100 μV
    (Maximum)
  • Zer? Drift: 0.35 μV/°C (Typical), 1.2 μV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 μA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI? Interface (10 MHz) With Daisy-Chain
    Capability
  • Rail-to-Rail Input and Output
  • Offset: 25 μV (Typical), 100 μV
    (Maximum)
  • Zer? Drift: 0.35 μV/°C (Typical), 1.2 μV/°C
    (Maximum)
  • Low Noise: 12 nV/√Hz
  • Input Offset Current: ±5 nA Maximum (25°C)
  • Gain Error: 0.1% Maximum (G ≥ 32),
    0.3% Maximum (G > 32)
  • Binary Gains: 1, 2, 4, 8, 16, 32, 64, 128 (PGA112,
    PGA116)
  • Scope Gains: 1, 2, 5, 10, 20, 50, 100, 200
    (PGA113, PGA117)
  • Gain Switching Time: 200 ns
  • 2 Channel MUX: PGA112, PGA113
    10 Channel MUX: PGA116, PGA117
  • Four Internal Calibration Channels
  • Amplifier Optimized for Driving CDAC ADCs
  • Output Swing: 50 mV to Supply Rails
  • AVDD and DVDD for Mixed Voltage Systems
  • IQ = 1.1 mA (Typical)
  • Software and Hardware Shutdown: IQ ≤ 4 μA
    (Typical)
  • Temperature Range: –40°C to 125°C
  • SPI? Interface (10 MHz) With Daisy-Chain
    Capability

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.

The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in a 10-pin, VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, a SPI interface with daisy-chain capability, and hardware and software shutdown in a 20-pin TSSOP package.

All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
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類型 標題 下載最新的英語版本 日期
* 數(shù)據(jù)表 PGA11x Zer?-Drift Programmable Gain Amplifier With Mux 數(shù)據(jù)表 (Rev. C) PDF | HTML 2015年 11月 30日
EVM 用戶指南 PGA112/113EVM Users Guide (Rev. A) 2012年 5月 17日
應用手冊 所選封裝材料的熱學和電學性質(zhì) 2008年 10月 16日

設(shè)計和開發(fā)

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評估板

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The PGA113EVM is an evaluation module that is used to fully evaluate the PGA113 programmable gain amplifier. The PGA113EVM consists of two printed circuit boards (PCBs). One board (the SM-USB-DIG Platform) generates the digital signals required to communicate with the PGA113. The second board is (...)

用戶指南: PDF
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支持軟件

SBOC272 — PGA112/113EVM Software

支持的產(chǎn)品和硬件

支持的產(chǎn)品和硬件

產(chǎn)品
可編程和可變增益放大器（PGA 和 VGA）
PGA112 — 具有 2 通道多路復用器的零溫漂、100μV 失調(diào)電壓、12nV/√Hz 噪聲、RRO（二進制增益）可編程增益放大器 PGA113 — 具有 2 通道多路復用器的零溫漂、100μV 失調(diào)電壓、12nV/√Hz 噪聲、RRO（范圍增益）可編程增益放大器
支持軟件

SBOC426 — PGA112/113EVM Source Code

支持的產(chǎn)品和硬件

支持的產(chǎn)品和硬件

產(chǎn)品
可編程和可變增益放大器（PGA 和 VGA）
PGA112 — 具有 2 通道多路復用器的零溫漂、100μV 失調(diào)電壓、12nV/√Hz 噪聲、RRO（二進制增益）可編程增益放大器 PGA113 — 具有 2 通道多路復用器的零溫漂、100μV 失調(diào)電壓、12nV/√Hz 噪聲、RRO（范圍增益）可編程增益放大器
模擬工具

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TINA-TI 提供了 SPICE 所有的傳統(tǒng)直流、瞬態(tài)和頻域分析以及更多。TINA 具有廣泛的后處理功能，允許您按照希望的方式設(shè)置結(jié)果的格式。虛擬儀器允許您選擇輸入波形、探針電路節(jié)點電壓和波形。TINA 的原理圖捕獲非常直觀 - 真正的“快速入門”。

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TINA 是德州儀器 (TI) 專有的 DesignSoft 產(chǎn)品。該免費版本具有完整的功能，但不支持完整版 TINA 所提供的某些其他功能。

如需獲取可用 TINA-TI 模型的完整列表，請參閱：SpiceRack - 完整列表 

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用戶指南: PDF
英語版 (Rev.A): PDF
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封裝 引腳 CAD 符號、封裝和 3D 模型
VSSOP (DGS) 10 Ultra Librarian

訂購和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標識
  • 引腳鍍層/焊球材料
  • MSL 等級/回流焊峰值溫度
  • MTBF/時基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測
包含信息：
  • 制造廠地點
  • 封裝廠地點

支持和培訓

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