CD4021B-Q1

正在供貨

汽車類 CMOS 8 級(jí)靜態(tài)移位寄存器

產(chǎn)品詳情

Configuration Serial-in, Parallel-out Bits (#) 8 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 8.5 IOL (max) (mA) 4.2 IOH (max) (mA) -4.2 Supply current (max) (μA) 3000 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -40 to 125 Rating Automotive
Configuration Serial-in, Parallel-out Bits (#) 8 Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Input type Standard CMOS Output type Push-Pull Clock frequency (MHz) 8.5 IOL (max) (mA) 4.2 IOH (max) (mA) -4.2 Supply current (max) (μA) 3000 Features Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns) Operating temperature range (°C) -40 to 125 Rating Automotive
SOIC (D) 16 59.4 mm2 9.9 x 6
  • Qualified for Automotive Applications
  • Medium-Speed Operation: 12-MHz (Typ) Clock Rate at VDD – VSS = 10 V
  • Fully Static Operation
  • Eight Master-Slave Flip-Flops Plus Output Buffering and Control Gating
  • 100% Tested for Quiescent Current at 20 V
  • Maximum Input Current of 1 μA at 18 V Over Full Package-Temperature Range:
    100 nA at 18 V and 25°C
  • Noise Margin (Full Package-Temperature Range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Standardized Symmetrical Output Characteristics
  • 5-V, 10-V, and 15-V Parametric Ratings
  • Meets All Requirements of JEDEC Tentative Standard No. 13B,
    "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Latch-Up Performance Meets 50 mA per JESD 78, Class I
  • APPLICATIONS
    • Parallel Input/Serial Output Data Queuing
    • Parallel-to-Serial Data Conversion
    • General-Purpose Register
  • Qualified for Automotive Applications
  • Medium-Speed Operation: 12-MHz (Typ) Clock Rate at VDD – VSS = 10 V
  • Fully Static Operation
  • Eight Master-Slave Flip-Flops Plus Output Buffering and Control Gating
  • 100% Tested for Quiescent Current at 20 V
  • Maximum Input Current of 1 μA at 18 V Over Full Package-Temperature Range:
    100 nA at 18 V and 25°C
  • Noise Margin (Full Package-Temperature Range):
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Standardized Symmetrical Output Characteristics
  • 5-V, 10-V, and 15-V Parametric Ratings
  • Meets All Requirements of JEDEC Tentative Standard No. 13B,
    "Standard Specifications for Description of ’B’ Series CMOS Devices"
  • Latch-Up Performance Meets 50 mA per JESD 78, Class I
  • APPLICATIONS
    • Parallel Input/Serial Output Data Queuing
    • Parallel-to-Serial Data Conversion
    • General-Purpose Register

CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.

The CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).

CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, "Q" outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.

The CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (D and F suffixes), 16-lead dual-in-line plastic packages (E suffix), and in chip form (H suffix).
下載 觀看帶字幕的視頻 視頻

您可能感興趣的相似產(chǎn)品

功能與比較器件相同，且具有相同引腳
SN74AC164-Q1 正在供貨 汽車級(jí) 1.5V 至 6V 8 位串行輸入并行輸出移位寄存器 Smaller voltage range (2V to 6V), shorter average propagation delay (7ns), higher average drive strength (24mA)

技術(shù)文檔

star =有關(guān)此產(chǎn)品的 TI 精選熱門(mén)文檔
未找到結(jié)果。請(qǐng)清除搜索并重試。
查看全部 11
類型 標(biāo)題 下載最新的英語(yǔ)版本 日期
* 數(shù)據(jù)表 CD4021B-Q1 CMOS 8-Stage Static Shift Register 數(shù)據(jù)表 2010年 3月 26日
應(yīng)用手冊(cè) Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
選擇指南 Logic Guide (Rev. AB) 2017年 6月 12日
應(yīng)用手冊(cè) Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
選擇指南 邏輯器件指南 2014 (Rev. AA) 最新英語(yǔ)版本 (Rev.AC) PDF | HTML 2014年 11月 17日
更多文獻(xiàn)資料 汽車邏輯器件 英語(yǔ)版 2014年 2月 5日
用戶指南 LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
應(yīng)用手冊(cè) Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
用戶指南 Signal Switch Data Book (Rev. A) 2003年 11月 14日
應(yīng)用手冊(cè) Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 2001年 12月 3日
選擇指南 Logic Guide (Rev. AC) PDF | HTML 1994年 6月 1日

設(shè)計(jì)和開(kāi)發(fā)

如需其他信息或資源，請(qǐng)點(diǎn)擊以下任一標(biāo)題進(jìn)入詳情頁(yè)面查看（如有）。

評(píng)估板

14-24-LOGIC-EVM — 采用 14 引腳至 24 引腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產(chǎn)品通用評(píng)估模塊

14-24-LOGIC-EVM 評(píng)估模塊 (EVM) 設(shè)計(jì)用于支持采用 14 引腳至 24 引腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯器件。

用戶指南: PDF | HTML
英語(yǔ)版 (Rev.B): PDF | HTML
TI.com 上無(wú)現(xiàn)貨
封裝 引腳 CAD 符號(hào)、封裝和 3D 模型
SOIC (D) 16 Ultra Librarian

訂購(gòu)和質(zhì)量

包含信息：
  • RoHS
  • REACH
  • 器件標(biāo)識(shí)
  • 引腳鍍層/焊球材料
  • MSL 等級(jí)/回流焊峰值溫度
  • MTBF/時(shí)基故障估算
  • 材料成分
  • 鑒定摘要
  • 持續(xù)可靠性監(jiān)測(cè)
包含信息：
  • 制造廠地點(diǎn)
  • 封裝廠地點(diǎn)

支持和培訓(xùn)

可獲得 TI 工程師技術(shù)支持的 TI E2E? 論壇

所有內(nèi)容均由 TI 和社區(qū)貢獻(xiàn)者按“原樣”提供，并不構(gòu)成 TI 規(guī)范。請(qǐng)參閱使用條款。

如果您對(duì)質(zhì)量、包裝或訂購(gòu) TI 產(chǎn)品有疑問(wèn)，請(qǐng)參閱 TI 支持。??????????????

視頻