SNVU753A November 2019 – May 2021 TPS542A52
The TPS542A52EVM-059 is provided with input/output connectors and test points as shown in Table 3-2. A power supply capable of supplying at least 5 A at the desired EVM input voltage must be connected to J1 through a pair of 20-AWG or greater wires. The load must be connected to J2 through a pair of 18-AWG or greater wires. The maximum load current capability is 15 A.
Wire lengths must be minimized to reduce losses and parasitic inductance in the wires. PVIN+ (TP1) provides a test point to monitor the VIN input voltages with PVIN- (TP2) providing a convenient reference to PGND. VOUT+ (TP6) is used to monitor the output voltage with VOUT- (TP7) providing a reference to PGND.
| CONNECTION AND TEST POINTS | DESCRIPTION |
|---|---|
| J1 | VIN, PGND connection (see Table 1-1 for input voltage range) |
| J2 | VOUT, PGND connection: 5.5 V at 15 A maximum (default is 1 V out at 15 A) |
| J3 | Programming mode and external clock synchronization |
| J4 | Enable configuration |
| J5 | Output current sensing points when using function generator as load control signal |
| J6 | Not utilized in this EVM |
| PVIN+ (TP1), PVIN- (TP2) | VIN voltage sensing test points |
| VOUT+ (TP6), VOUT- (TP7) | VOUT voltage sensing test points |
| AVIN (TP3) | AVIN voltage sensing test points |
| VREG (TP4) | VREG voltage sensing test point |
| SW+ (TP5), SW- (TP18) | SW node sensing test points |
| CHA (TP9), CHB (TP8) | Loop measurement test points |
| EN (TP10) | EN pin test point |
| PGD (TP11) | Open-drain PGD test point |
| SYNC_CLK (TP12) | For connecting and measuring external clock synchronization |
| AGND (TP13, TP14, TP15) | AGND connection - multiple provided to reduce oscilloscope ground probe loop inductance |
| PGND (TP17) | PGND connection |
| FGEN+ (TP19), FGEN- (TP20) | Function generator connection points - referenced to PGND |