SLVK226 October 2025 TPS7H4012-SEP
The TPS7H401x-SEP is fabricated in the TI Linear BiCMOS 250-nm process with a back-end-of-line (BEOL) stack consisting of four levels of standard thickness aluminum and Damascene copper. The total stack height from the surface of the passivation to the silicon surface is 13.5 μm based on nominal layer thickness as shown in Figure 5-1. Accounting for energy loss through the degrader, copper foil, beam port window, air gap, and the BEOL stack of the TPS7H401x-SEP, the effective LET (LETEFF) at the surface of the silicon substrate and the depth was determined with:
The results are shown in Table 5-1.
|
Facility |
Ion Type | Beam Energy (MeV/nucleon) | Degrader Steps (#) | Degrader Angle |
Copper Foil Width (μm) |
Beam Port Window |
Air Gap (mm) |
Angle of Incidence |
LETEFF (MeV·cm2/ mg) | Range in Silicon (μm) |
|---|---|---|---|---|---|---|---|---|---|---|
|
TAMU |
109Ag | 15 | 0 | 0 |
- |
1-mil Aramica |
40 |
0 |
48.2 |
91.6 |
|
KSEE |
109Ag |
19.5 |
- |
- |
5 |
3-mil PEN |
60 |
0 |
48 |
89.3 |