SLAAEM4 October 2025 TAS2120 , TAS2320
When the noise gate feature is enabled, the device automatically detects periods of silence during active playback mode and reduces the idle channel power consumption significantly to extend the battery life. This feature is particularly effective for audio content with extended quiet intervals, such as voice calls or movie soundtracks.
The device monitors the input audio level against a threshold defined in the NG_TH_LVL[2:0] register. When the audio signal falls below the threshold, an internal hysteresis timer is enabled. If the signal level remains below the configured NG_TH_LVL[2:0] threshold for the entire duration of the NG_HYST_TIMER[1:0] timer, the device enters the noise gate mode and reduces the idle channel power consumption. In this state, high-power switching blocks, including the Class-D PWM output stage, are shut down and the outputs are driven low. The output impedance of the Class-D stage, while in noise gate mode, can be configured through the CLASSD_HIZ_MODE register, allowing designers to improve system behavior depending on load requirements. When the device is in noise gate mode, the NG_STATUS bit is set as high and when the device comes out of noise gate mode, the status bit is set to low.
When the signal level increases above the NG_TH_LVL[1:0] threshold, the device automatically wakes up the blocks in low IQ mode and starts playing out the audio input signals. The wake up from noise gate maintains the signal fidelity by buffering the input signal data during the transition time from noise gate mode to active playback mode. The return to active playback is designed with proper sequencing to avoid audible clicks or pops, maintaining signal fidelity throughout.
The noise gate feature reduces idle current without compromising playback quality, while giving system designers precise control of threshold, hysteresis timing, and output impedance behavior through register configuration.
| NG_TH_LVL[2:0] | Configuration |
|---|---|
| 000 | -85dBFs |
| 001 | -90dBFs |
| 010 | -95dBFs |
| 011 | -100dBFs |
| 100 (default) | -105dBFs |
| 101 | -110dBFs |
| 110 | -115dBFs |
| 111 | -120dBFs |
| NG_HYST_TIMER[1:0] | Configuration |
|---|---|
| 00 | 10ms |
| 01 (default) | 50ms |
| 10 | 100ms |
| 11 | 1000ms |
Both music efficiency mode and noise gate mode are controlled through the EFFICIENCY_MODE[1:0] register, which allows configuration of the desired efficiency mode of operation.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | EFFICIENCY_MODE[1:0] | R/W | 2h | Device operational mode. 0h = Music efficiency and noise gate mode disabled 1h = Noise gate mode only 2h = Music efficiency only 3h = Music efficiency and noise gate mode |