ZHCSIQ7B August 2018 – October 2024 UCC28950 , UCC28951
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Start-Up Protection Logic
- 6.3.2 Voltage Reference (VREF)
- 6.3.3 Error Amplifier (EA+, EA–, COMP)
- 6.3.4 Soft-Start and Enable (SS/EN)
- 6.3.5 Light-Load Power Saving Features
- 6.3.6 Adaptive Delay, (Delay Between OUTA and OUTB, OUTC and OUTD (DELAB, DELCD, ADEL))
- 6.3.7 Adaptive Delay (Delay Between OUTA and OUTF, OUTB and OUTE (DELEF, ADELEF)
- 6.3.8 Minimum Pulse (TMIN)
- 6.3.9 Burst Mode
- 6.3.10 Switching Frequency Setting
- 6.3.11 Slope Compensation (RSUM)
- 6.3.12 Dynamic SR ON/OFF Control (DCM Mode)
- 6.3.13 Current Sensing (CS)
- 6.3.14 Cycle-by-Cycle Current Limit Current Protection and Hiccup Mode
- 6.3.15 Synchronization (SYNC)
- 6.3.16 Outputs (OUTA, OUTB, OUTC, OUTD, OUTE, OUTF)
- 6.3.17 Supply Voltage (VDD)
- 6.3.18 Ground (GND)
- 6.4 Device Functional Modes
-
7 Application and Implementation
- 7.1 Application Information
- 7.2
Typical Application
- 7.2.1 Design Requirements
- 7.2.2
Detailed Design Procedure
- 7.2.2.1 Power Loss Budget
- 7.2.2.2 Preliminary Transformer Calculations (T1)
- 7.2.2.3 QA, QB, QC, QD FET Selection
- 7.2.2.4 Selecting LS
- 7.2.2.5 Selecting Diodes DB and DC
- 7.2.2.6 Output Inductor Selection (LOUT)
- 7.2.2.7 Output Capacitance (COUT)
- 7.2.2.8 Select FETs QE and QF
- 7.2.2.9 Input Capacitance (CIN)
- 7.2.2.10 Current Sense Network (CT, RCS, R7, DA)
- 7.2.3 Application Curves
- 7.3 Power Supply Recommendations
- 7.4 Layout
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- PW|24
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.2.2.7 Output Capacitance (COUT)
The output capacitor is selected based on holdup and transient (VTRAN) load requirements.
The time it takes LOUT to change 90% of its full load current is calculated in Equation 67:
During load transients most of the current will immediately go through the capacitors equivalent series resistance (ESRCOUT). Equation 68 and Equation 69 are used to select ESRCOUT and COUT based on a 90% load step in current. The ESR is selected for 90% of the allowable transient voltage (VTRAN), while the output capacitance (COUT) is selected for 10% of VTRAN.
Before selecting the output capacitor, the output capacitor RMS current (ICOUT_RMS) must be calculated using Equation 70.
To meet the design requirements five 1500μF, aluminum electrolytic capacitors are chosen for the design from United Chemi-Con?, part number EKY-160ELL152MJ30S. These capacitors have an ESR of 31mΩ.
The number of output capacitors (n) is 5.
The total output capacitance is calculated usingEquation 71:
The effective output capacitance ESR is calculated usingEquation 72:
Calculate output capacitor loss (PCOUT) using Equation 73:
Recalculate the remaining Power Budget using Equation 74:
