ZHCSAW2E February 2013 – December 2014 UCC28251
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 VDD (5/12)
- 8.3.2 VREF (Reference Generator) (20/7)
- 8.3.3 EN (Enable Pin) (18/5)
- 8.3.4 RT (Oscillator Frequency Set and Synchronization) (15/2)
- 8.3.5 SP (Synchronous Rectifier Turn-Off to Primary Output Turn-On Dead Time Programming) (13/19)
- 8.3.6 PS (Primary Output Turn-Off to Synchronous Rectifier Turn-On Dead Time Programming) (11/18)
- 8.3.7 RAMP/CS (PWM Ramp Input or Current Sense Input) (16/3)
- 8.3.8 REF/EA+ (1/8)
- 8.3.9 FB/EA- (2/9)
- 8.3.10 COMP (3/10)
- 8.3.11 VSENSE (14/1)
- 8.3.12 SS (Soft Start Programming Pin) (13/20)
- 8.3.13 ILIM (Current Limit for Cycle-by-Cycle Over-Current Protection) (17/4)
- 8.3.14 HICC (10/17)
- 8.3.15 OVP/OTP (19/6)
- 8.3.16 OUTA (9/16) and OUTB (8/15)
- 8.3.17 SRA (7/14) and SRB (6/13)
- 8.3.18 GND (4/11)
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1
Circuit Diagram in Design Example
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Step 1: Power Stage Design
- 9.2.1.2.2 Step 2: Feedback Loop Design
- 9.2.1.2.3 Step 3: Programming The Device
- 9.2.1.2.4 Step 3-3: Determine Soft-Start Capacitance
- 9.2.1.2.5 Step 3-4: Determine Dead-Time Resistance
- 9.2.1.2.6 Step 3-5: Determine OCP Hiccup Off-Time Capacitance
- 9.2.1.2.7 Step 3-6: Determine Primary-Side OVP Resistance
- 9.2.1.2.8 Step 3-7: Select Capacitance for VDD and VREF
- 9.2.1.3 Application Curves
- 9.2.2 Secondary-Side Half-Bridge Controller With Synchronous Rectification
- 9.2.1
Circuit Diagram in Design Example
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械、封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGP|20
訂購信息
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range(1)(2) (unless otherwise noted)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VDD(3) | Input supply voltage | –0.3 | 20 | V |
| OUTA, OUTB, SRA and SRB | –0.3 | VDD + 0.3 | ||
| COMP | –0.3 | VREF + 0.3 | ||
| Input voltages on SS and EN | –0.3 | 5.5 | ||
| Input voltages on RT, PS, SP, ILIM, OVP, HICC, VSENSE, EA+ and EA- | –0.3 | 3.6 | ||
| Input voltage on RAMP/CS | –0.3 | 4.3 | ||
| Output voltage on VREF | –0.3 | 3.6 | ||
| Lead temperature (soldering 10 sec) PW package | 300 | °C | ||
| Tstg | Storage temperature | –65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.
(3) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified pin. See Packaging Section of the datasheet for thermal limitations and considerations of packages.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±3000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±2000 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)7.4 Thermal Information
| THERMAL METRIC(1) | UCC28251 | UNIT | ||
|---|---|---|---|---|
| RGP | PW | |||
| 20 PINS | 20 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 126 with hot spot, 104 without hot spot |
60.3 with hot spot, 39.3 without hot spot |
°C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | N/A | 31.5 | |
| RθJB | Junction-to-board thermal resistance | N/A | 55.8 | |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 0.8 | N/A | |
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics(1)
VDD = 12 V, 1-µF capacitor from VDD and VREF to GND, TA = TJ = –40°C to 125°C, RT = 75 kΩ connected to ground to set FSW = 100 kHz (unless otherwise noted).| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY CURRENTS | ||||||
| IDD(off) | Startup current | VDD = 3.6 V | 150 | 275 | µA | |
| IDD | Operating supply current | 100-pF capacitor on OUTA, OUTB, SRA and SRB | 1.2 | 2.0 | 2.5 | mA |
| IDD(dis) | Standby current | EN = 0 V | 250 | 425 | 600 | µA |
| UNDERVOLTAGE LOCKOUT | ||||||
| VUVLOR | Start threshold | 4.00 | 4.30 | 4.65 | V | |
| VUVLOF | Minimum operating voltage after start | 3.8 | 4.1 | 4.4 | ||
| Hysteresis | 0.15 | 0.20 | 0.25 | |||
| SOFT-START | ||||||
| ISS | Soft-start charge current | VSS = 0 V | 26 | 28 | 30 | µA |
| VSS(max) | Clamp voltage | 3.3 | 3.6 | 4.0 | V | |
| ENABLE(2) | ||||||
| Trigger threshold | 1.5 | 2.0 | 2.25 | V | ||
| Minimum pulse width for pulse enable | 3.2 | µs | ||||
| ERROR AMPLIFIER | ||||||
| High-level COMP voltage | 2.8 | 3 | V | |||
| Low-level COMP voltage | 0.3 | 0.4 | ||||
| Input offset | –16.2 | 18.0 | mV | |||
| Open loop gain | 70 | 100 | dB | |||
| ICOMP(snk) | COMP sink current | 3.0 | 6.5 | 9.0 | mA | |
| ICOMP(src) | COMP source current | 2.0 | 4.5 | 8.0 | ||
| OSCILLATOR | ||||||
| FSW(nom) | Nominal switching frequency at OUTA or OUTB set by RT resistor | RT/SYNC = 75 kΩ, RSP = 20 kΩ | 90 | 98 | 106 | kHz |
| FSW(min_sync) | Minimum switching frequency at OUTA or OUTB set by external sync frequency | fRT/SYNC = 50 kHz | 42 | |||
| FSW(max_sync) | Maximum switching frequency at OUTA or OUTB set by external sync frequency | fRT/SYNC = 2.5 MHz | 945 | |||
| External synchronization signal high | 1 | V | ||||
| External synchronization signal low | 0.2 | |||||
| VOLTAGE REFERENCE | ||||||
| VVREF | Output voltage | VDD = from 7 V to 17 V, IVREF = 2 mA | 3.17 | 3.25 | 3.33 | V |
| 0 < IREF < 10 mA | 3.17 | 3.25 | 3.33 | |||
| Short circuit current | VREF = 3 V, TJ = 25 °C | 12 | 25 | 40 | mA | |
| CURRENT SENSE, CYCLE-BY-CYCLE CURRENT LIMIT WITH HICCUP | ||||||
| VILIM | ILIM cycle-by-cycle threshold | 0.497 | 0.505 | 0.513 | V | |
| TPDILIM | Propagation delay from ILIM to OUTA and OUTB outputs | Exclude leading edge blanking (UCC28251RGP) | 15 | 25 | 36 | ns |
| Exclude leading edge blanking (UCC28251PW) | 12.3 | 25.0 | 38.7 | |||
| TBLANK | Leading edge blanking | 35 | 60 | 90 | ||
| Current limit shutdown delay timing program current | Measured at HICC pin | 55 | 75 | 95 | µA | |
| Hiccup timing program current | Measured at HICC pin | 2.0 | 2.7 | 3.5 | ||
| VHICC_SD | Current limit shutdown delay timer threshold at HICC | 0.55 | 0.60 | 0.65 | V | |
| VHICC_PU | HICC pull-up threshold | 2.25 | 2.40 | 2.50 | ||
| VHICC_RST | Hiccup restart threshold | 0.25 | 0.30 | 0.35 | ||
| VCS(max) | RAMP/CS clamp voltage | 10-V ramp charging voltage source with 40-kΩ current limiting resistor | 3.5 | 4.0 | 4.5 | |
| OVP/OTP COMPARATOR | ||||||
| VOVP | Internal reference | 0.66 | 0.70 | 0.74 | V | |
| IOVP | Internal current | 6.0 | 8.5 | 11.0 | µA | |
| PRIMARY OUTPUTS | ||||||
| Rise/fall time | CLOAD = 100 pF | 8 | ns | |||
| RSRC | Output source resistance | IOUT = 20 mA | 12 | 20 | 35 | Ω |
| RSNK | Output sink resistance | IOUT = 20 mA | 4 | 12 | 30 | |
| SYNCHRONOUS RECTIFIER OUTPUTS | ||||||
| Rise/fall time | CLOAD = 100 pF | 8 | ns | |||
| RSRC | Output source resistance | IOUT = 20 mA, VDD = 12 V | 12 | 20 | 35 | Ω |
| IOUT = 20 mA, VDD = 5 V | 15 | 25 | 45 | |||
| RSNK | Output sink resistance | IOUT = 20 mA, VDD = 12 V | 4 | 12 | 30 | |
| TDPS | Primary off to secondary on dead time | PS = VREF | –5.0 | 0 | 7.5 | ns |
| PS = 27 kΩ | 25 | 38 | 48 | |||
| PS = 27 kΩ, 25 °C | 32 | 38 | 43 | |||
| TDSP | Secondary off to primary on dead time | SP = VREF | –5.0 | 0 | 7.5 | ns |
| SP = 20 kΩ | 33 | 43 | 55 | |||
| SP = 20 kΩ, 25 °C | 39 | 43 | 48 | |||
(1) Typical values for TA = 25 °C.
(2) Refer to EN pin description.
7.6 Typical Characteristics
Figure 1. Start-Up Current vs Temperature
Figure 3. UVLO Thresholds vs Temperature
Figure 5. Operating Supply Current vs Temperature
_lusbd8.png "UCC28251 Reference Voltage
vs Temperature")
Figure 11. Reference Voltage vs Temperature
Figure 13. OVP Internal Reference vs Temperature
Figure 15. Minimum Synchronization Frequency vs Temperature
Figure 17. Nominal Switching Frequency vs Temperature
Figure 19. Output Rise/Fall Time vs Temperature
Figure 2. Stand-By Current vs Temperature
Figure 4. UVLO Voltage Lockout Hysteresis vs Temperature
Figure 6. Soft-Start Current vs Temperature
Figure 8. RAMP/CS Clamp Voltage and Hiccup Pull-Up Threshold vs Temperature
Figure 10. Current Limit Shutdown Delay Timer and Hiccup Restart vs Temperature
_lusbd8.png "UCC28251 Reference Voltage
vs Temperature")
Figure 12. Reference Voltage vs Temperature
Figure 14. OVP Internal Current vs Temperature
Figure 16. Maximum Synchronization Frequency vs Temperature
Figure 18. Dead Time vs Temperature
Figure 20. Output Source Resistance/Sink Resistance vs Temperature