ZHCSAW2E February 2013 – December 2014 UCC28251
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續(xù)）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 VDD (5/12)
- 8.3.2 VREF (Reference Generator) (20/7)
- 8.3.3 EN (Enable Pin) (18/5)
- 8.3.4 RT (Oscillator Frequency Set and Synchronization) (15/2)
- 8.3.5 SP (Synchronous Rectifier Turn-Off to Primary Output Turn-On Dead Time Programming) (13/19)
- 8.3.6 PS (Primary Output Turn-Off to Synchronous Rectifier Turn-On Dead Time Programming) (11/18)
- 8.3.7 RAMP/CS (PWM Ramp Input or Current Sense Input) (16/3)
- 8.3.8 REF/EA+ (1/8)
- 8.3.9 FB/EA- (2/9)
- 8.3.10 COMP (3/10)
- 8.3.11 VSENSE (14/1)
- 8.3.12 SS (Soft Start Programming Pin) (13/20)
- 8.3.13 ILIM (Current Limit for Cycle-by-Cycle Over-Current Protection) (17/4)
- 8.3.14 HICC (10/17)
- 8.3.15 OVP/OTP (19/6)
- 8.3.16 OUTA (9/16) and OUTB (8/15)
- 8.3.17 SRA (7/14) and SRB (6/13)
- 8.3.18 GND (4/11)
- 8.4 Device Functional Modes
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Applications
- 9.2.1
Circuit Diagram in Design Example
- 9.2.1.1 Design Requirements
- 9.2.1.2
Detailed Design Procedure
- 9.2.1.2.1 Step 1: Power Stage Design
- 9.2.1.2.2 Step 2: Feedback Loop Design
- 9.2.1.2.3 Step 3: Programming The Device
- 9.2.1.2.4 Step 3-3: Determine Soft-Start Capacitance
- 9.2.1.2.5 Step 3-4: Determine Dead-Time Resistance
- 9.2.1.2.6 Step 3-5: Determine OCP Hiccup Off-Time Capacitance
- 9.2.1.2.7 Step 3-6: Determine Primary-Side OVP Resistance
- 9.2.1.2.8 Step 3-7: Select Capacitance for VDD and VREF
- 9.2.1.3 Application Curves
- 9.2.2 Secondary-Side Half-Bridge Controller With Synchronous Rectification
- 9.2.1
Circuit Diagram in Design Example
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
- RGP|20
訂購信息
12 器件和文檔支持
12.1 文檔支持
12.2 商標
All trademarks are the property of their respective owners.
12.3 靜電放電警告
這些裝置包含有限的內(nèi)置 ESD 保護。 存儲或裝卸時，應將導線一起截短或將裝置放置于導電泡棉中，以防止 MOS 門極遭受靜電損傷。
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.