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SLUS828D December 2008 – October 2017 UCC28019A

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

D|8
- MSOI002K

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range unless otherwise noted. Unless noted, all voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.

		MIN	MAX	UNIT
Input voltage range	VCC, GATE	–0.3	22	V
	VINS, VSENSE,	–0.3	7	V
	VCOMP, ICOMP⁽²⁾	–0.3	7.5	V
	ISENSE	–24	7	V
Input current range	VSENSE, ISENSE	–1	1	mA
Lead temperature, T_SOL	Soldering, 10s		300	°C
Junction temperature, T_J	Operating	–55	150	°C
Junction temperature, T_J	Storage	–65	150	°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those included under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.

(2) The VCOMP and ICOMP pin can go to 7.5 V ±6% due to internal drive circuitry. Absolute maximum rating is 7 V when an external bias is applied to the pin, with the source current limited below 50 µA.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
VCC input voltage from a low-impedance source	VCC_OFF + 1 V	21	V
Operating junction temperature, T_J	-40	125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC28019A		UNIT
		P (PDIP)	D (SOIC)
		8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	52.8	113.0	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	42.3	61.5	°C/W
R_θJB	Junction-to-board thermal resistance	30.0	53.2	°C/W
ψ_JT	Junction-to-top characterization parameter	19.5	15.9	°C/W
ψ_JB	Junction-to-board characterization parameter	29.9	52.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Unless otherwise noted, VCC=15 V_DC, 0.1 μF from VCC to GND, -40°C ≤ T_J = T_A ≤ 125°C. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.

PARAMETER		TEST CONDITION	MIN	TYP	MAX	UNIT
VCC Bias Supply
ICC_PRESTART	ICC pre-start current	VCC = VCC_ON – 0.1 V	25	100	200	μA
ICC_STBY	ICC standby current	VSENSE = 0.5 V	1	2.2	2.9	mA
ICC_{ON_load}	ICC operating current	VSENSE = 4.5 V, C_GATE = 4.7 nF	4	7.5	10	mA
Under Voltage Lockout (UVLO)
VCC_ON	VCC turn on threshold		10	10.5	11	V
VCC_OFF	VCC turn off threshold		9	9.5	10	V
	UVLO hysteresis		0.8	1	1.2	V
Oscillator
f_SW	Switching frequency	T_A = 25°C	61.7	65	68.3	kHz
		-25°C ≤ T_A ≤ 125°C	59	65	71	kHz
		-40°C ≤ T_A ≤ 125°C	57		71	kHz
PWM
D_MIN	Minimum duty cycle	VCOMP = 0 V, VSENSE = 5 V, ICOMP = 6.4 V			0%
D_MAX	Maximum duty cycle	VSENSE = 4.95 V	94%	98%	99.3%
t_OFF(min)	Minimum off time	VSENSE = 3 V, ICOMP = 1 V	100	250	600	ns
System Protection
V_SOC	ISENSE threshold, Soft Over Current (SOC)		-0.66	-0.73	-0.79	V
V_PCL	ISENSE threshold, Peak Current Limit (PCL)		-1	-1.08	-1.15	V
I_ISOP	ISENSE bias current, ISENSE Open-Pin Protection (ISOP)	ISENSE = 0 V		-2.1	-4.0	μA
V_ISOP	ISENSE threshold, ISENSE Open-Pin Protection (ISOP)	ISENSE = open pin		0.082		V
V_OLP	VSENSE threshold, Open Loop Protection (OLP)	ICOMP = 1 V, ISENSE = -0.1 V, VCOMP = 1 V	0.77	0.82	0.86	V
	Open Loop Protection (OLP) Internal pull-down current	VSENSE = 0.5 V		100	250	nA
V_UVD	VSENSE threshold, output Under-Voltage Detection (UVD)⁽¹⁾		4.63	4.75	4.87	V
V_OVP	VSENSE threshold, output Over-Voltage Protection (OVP)	ISENSE = -0.1 V	5.12	5.25	5.38	V
V_{INSBROWNOUT_th}	Input Brown-Out Detection (IBOP) high-to-low threshold		0.76	0.82	0.88	V
V_{INSENABLE_th}	Input Brown-Out Detection (IBOP) low-to-high threshold		1.4	1.5	1.6	V
I_{VINS_0V}	VINS bias current	VINS = 0 V		0	±0.1	μA
	ICOMP threshold, external overload protection			0.6		V
Current Loop
g_mi	Transconductance gain	T_A = 25°C	0.75	0.95	1.15	mS
	Output linear range⁽¹⁾			±50		μA
	ICOMP voltage during OLP	VSENSE = 0.5 V	3.7	4	4.3	V
Voltage Loop
V_REF	Reference voltage	-40°C ≤ T_A ≤ 125°C	4.9	5	5.1	V
g_mv	Transconductance gain without EDR		-31.5	-42	-52.5	μS
g_mv-EDR	Transconductance gain under EDR	VSENSE = 4.65 V		-440		μS
	Maximum sink current under normal operation	VSENSE = 6 V, VCOMP = 4 V	21	30	38	μA
	Source current under soft start	VSENSE = 4 V, VCOMP = 2.5 V	-21	-30	-38	μA
	Maximum source current under EDR operation	VSENSE = 4 V, VCOMP = 2.5 V		-300		μA
	Maximum source current under EDR operation	VSENSE = 4 V, VCOMP = 4 V		-170		μA
	Enhanced dynamic response VSENSE low threshold, falling⁽¹⁾		4.63	4.75	4.87	V
	VSENSE input bias current	VSENSE = 5 V	20	100	250	nA
	VCOMP voltage during OLP	VSENSE = 0.5 V, I_VCOMP = 0.5 mA	0	0.2	0.4	V
	VCOMP rapid discharge current	VCOMP = 3 V, VCC = 0 V		0.77		mA
V_PRECHARGE	VCOMP precharge voltage	I_VCOMP = -100 μA, VSENSE = 5 V		1.76		V
I_PRECHARGE	VCOMP precharge current	VCOMP = 1.0 V		-1		mA
	VSENSE threshold, end of soft start	Initial start up		4.95		V
GATE Driver
	GATE current, peak, sinking⁽¹⁾	C_GATE = 4.7 nF		2		A
	GATE current, peak, sourcing⁽¹⁾	C_GATE = 4.7 nF		-1.5		A
	GATE rise time	C_GATE = 4.7 nF, GATE = 2 V to 8 V	8	40	60	ns
	GATE fall time	C_GATE = 4.7 nF, GATE = 8 V to 2 V	8	25	40	ns
	GATE low voltage, no load	I _GATE = 0 A		0	0.05	V
	GATE low voltage, sinking	I _GATE = 20 mA		0.3	0.8	V
	GATE low voltage, sourcing	I _GATE = -20 mA		-0.3	-0.8	V
	GATE low voltage, sinking, device OFF	VCC = 5 V, I_GATE = 5 mA	0.2	0.75	1.2	V
	GATE low voltage, sinking, device OFF	VCC = 5 V, I_GATE = 20 mA	0.2	0.9	1.5	V
	GATE high voltage	VCC = 20 V, C_GATE = 4.7 nF	11.0	12.5	14.0	V
		VCC = 11 V, C_GATE = 4.7 nF	9.5	10.5	11.0	V
		VCC = VCC_OFF + 0.2 V, C_GATE = 4.7 nF	8.0	9.4	10.2	V

(1) Not production tested. Characterized by design.

6.6 Typical Characteristics

Unless otherwise noted, VCC = 15 V_DC, 0.1 μF from VCC to GND, -40°C ≤ T_J = T_A ≤ 125°C. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.