SLUS828D December 2008 – October 2017 UCC28019A
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Soft-Start
- 7.3.2
System Protection
- 7.3.2.1 VCC Undervoltage Lockout (UVLO)
- 7.3.2.2 Input Brown-Out Protection (IBOP)
- 7.3.2.3 Output Overvoltage Protection (OVP)
- 7.3.2.4 Open Loop Protection/Standby (OLP/Standby)
- 7.3.2.5 ISENSE Open-Pin Protection (ISOP)
- 7.3.2.6 Output Undervoltage Detection (UVD) and Enhanced Dynamic Response (EDR)
- 7.3.2.7 Over-Current Protection
- 7.3.2.8 Soft Over Current (SOC)
- 7.3.2.9 Peak Current Limit (PCL)
- 7.3.2.10 Current Sense Resistor, RISENSE
- 7.3.3 Gate Driver
- 7.3.4 Current Loop
- 7.3.5 ISENSE and ICOMP Functions
- 7.3.6 Pulse Width Modulator
- 7.3.7 Control Logic
- 7.3.8 Voltage Loop
- 7.3.9 Output Sensing
- 7.3.10 Voltage Error Amplifier
- 7.3.11 Non-Linear Gain Generation
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
5 Pin Configuration and Functions
D, P Package
8-Pin SOIC, 8-Pin PDIP
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| SOIC, PDIP | |||
| GND | 1 | — | Ground: device ground reference. |
| ICOMP | 2 | O | Current loop compensation: Transconductance current amplifier output. A capacitor connected to GND provides compensation and averaging of the current sense signal in the current control loop. The controller is disabled if the voltage on ICOMP is less than 0.6 V. |
| ISENSE | 3 | I | Inductor current sense: Input for the voltage across the external current sense resistor, which represents the instantaneous current through the PFC boost inductor. This voltage is averaged by the current amplifier to eliminate the effects of ripple and noise. Soft Over Current (SOC) limits the average inductor current. Cycle-by-cycle Peak Current Limit (PCL) immediately shuts off the GATE drive if the peak-limit voltage is exceeded. An internal 1.5-μA current source pulls ISENSE above 0.1 V to shut down PFC operation if this pin becomes open-circuited. Use a 220-Ω resistor between this pin and the current sense resistor to limit inrush-surge currents into this pin. |
| VINS | 4 | I | Input ac voltage sense: A filtered resistor-divider network connects from this pin to the rectified-mains node. Input Brown-Out Protection (IBOP) detects when the system ac-input voltage is above a user-defined normal operating level, or below a user-defined “brown-out” level. At startup the controller is disabled until the VINS voltage exceeds a threshold of 1.5 V, initiating a soft start. The controller is also disabled if VINS drops below the brown-out threshold of 0.8 V. Operation will not resume until both VINS and VSENSE voltages exceed their enable thresholds, initiating another soft start. |
| VCOMP | 5 | O | Voltage loop compensation: Transconductance voltage error amplifier output. A resistor-capacitor network connected from this pin to GND provides compensation. VCOMP is held at GND until VCC, VINS, and VSENSE all exceed their threshold voltages. Once these conditions are satisfied, VCOMP is charged until the VSENSE voltage reaches 99% of its nominal regulation level. When Enhanced Dynamic Response (EDR) is engaged, a higher transconductance is applied to VCOMP to reduce the charge time for faster transient response. Soft Start is programmed by the capacitance on this pin. The EDR higher transconductance is inhibited during Soft Start. |
| VSENSE | 6 | I | Output voltage sense: An external resistor-divider network connected from this pin to the PFC output voltage provides feedback sensing for regulation to the internal 5-V reference voltage. A small capacitor from this pin to GND filters high-frequency noise. Standby mode disables the controller and discharges VCOMP when the voltage at VSENSE drops below the enable threshold of 0.8 V. An internal 100-nA current source pulls VSENSE to GND for Open-Loop Protection (OLP), including pin disconnection. Output Over-Voltage Protection (OVP) disables the GATE output when VSENSE exceeds 105% of the reference voltage. Enhanced Dynamic Response (EDR) rapidly returns the output voltage to its normal regulation level when a system line or load step causes VSENSE to fall below 95% of the reference voltage. |
| VCC | 7 | Device supply: External bias supply input. Under-Voltage Lockout (UVLO) disables the controller until VCC exceeds a turn-on threshold of 10.5 V. Operation continues until VCC falls below the turn-off (UVLO) threshold of 9.5 V. A ceramic by-pass capacitor of 0.1 μF minimum value should be connected from VCC to GND as close to the device as possible for high frequency filtering of the VCC voltage. | |
| GATE | 8 | O | Gate drive: Integrated push-pull gate driver for one or more external power MOSFETs. Typical 2.0-A sink and 1.5-A source capability. Output voltage is typically clamped at 12.5 V. |