ZHCSGH5D August 2017 – May 2019 TUSB1042I
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Supply Characteristics
- 6.6 DC Electrical Characteristics
- 6.7 AC Electrical Characteristics
- 6.8 DCI Specific Electrical Characteristics
- 6.9 Timing Requirements
- 6.10 Switching Characteristics
- 6.11 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Maps
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- RNQ|40
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.4.5 Operation Timing – Power Up
Figure 14. Power-Up Timing Table 6. Power-Up Timing(1)(2)
| PARAMETER | MIN | MAX | UNIT | |
|---|---|---|---|---|
| td_pg | VCC (minimum) to Internal Power Good asserted high | 500 | µs | |
| tcfg_su | CFG(1) pins setup(2) | 250 | µs | |
| tcfg_hd | CFG(1) pins hold | 10 | µs | |
| tCTL_DB | TEST1, CTL0 and FLIP pin debounce | 16 | ms | |
| tVCC_RAMP | VCC supply ramp requirement | 100 | ms |
(1) Following pins comprise CFG pins: I2C_EN, EQ[1:0], and SSEQ[1:0].
(2) Recommend CFG pins are stable when VCC is at min.