ZHCSGH5D August 2017 – May 2019 TUSB1042I
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| I2C (Refer to Figure 9) | ||||||
| fSCL | I2C clock frequency | 1 | MHz | |||
| tBUF | Bus free time between START and STOP conditions | 0.5 | µs | |||
| tHDSTA | Hold time after repeated START condition. After this period, the first clock pulse is generated | 0.26 | µs | |||
| tLOW | Low period of the I2C clock | 0.5 | µs | |||
| tHIGH | High period of the I2C clock | 0.26 | µs | |||
| tSUSTA | Setup time for a repeated START condition | 0.26 | µs | |||
| tHDDAT | Data hold time | 0 | μs | |||
| tSUDAT | Data setup time | 50 | ns | |||
| tR | Rise time of both SDA and SCL signals | 120 | ns | |||
| tF | Fall time of both SDA and SCL signals | 20 × (V(I2C)/5.5 V) | 120 | ns | ||
| tSUSTO | Setup time for STOP condition | 0.26 | μs | |||
| Cb | Capacitive load for each bus line | 150 | pF | |||