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SCDS256A October 2009 – September 2016 TS3USB31E

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RSE|8
- MPQF207E

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage		–0.5	7	V
V_IN	Control input voltage⁽²⁾⁽³⁾		–0.5	7	V
V_I/O	Switch I/O voltage ⁽²⁾⁽³⁾⁽⁴⁾	HSD+, HSD–	–0.5	V_CC + 0.3	V
		D+, D– when V_CC > 0	–0.5	V_CC + 0.3
		D+, D– when V_CC = 0		5.25
I_IK	Control input clamp current	V_IN< 0		–50	mA
I_I/OK	I/O port clamp current	V_I/O< 0		–50	mA
I_I/O	ON-state switch current⁽⁵⁾			±64	mA
	Continuous current through V_CC or GND			±100	mA
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to ground, unless otherwise specified.

(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(4) V_I and V_O are used to denote specific conditions for V_I/O.

(5) I_I and I_O are used to denote specific conditions for I_I/O.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±8000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

			MIN	MAX	UNIT
V_CC	Supply voltage		2.25	4.3	V
V_IH	High-level control input voltage	V_CC = 2.3 V to 2.7 V	0.9		V
		V_CC = 3 V to 3.6 V	1.3
		V_CC = 4.3 V	1.7
V_IL	Low-level control input voltage	V_CC = 2.3 V to 2.7 V		0.4	V
		V_CC = 3 V to 3.6 V		0.5
		V_CC = 4.3 V		0.7
V_I/O	Data input-output voltage		0	V_CC	V
T_A	Operating free-air temperature		–40	85	°C

(1) All unused control inputs of the device must be held at V_CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TS3USB31	UNIT
		RSE (UQFN)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	127.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	70.4	°C/W
R_θJB	Junction-to-board thermal resistance	35	°C/W
ψ_JT	Junction-to-top characterization parameter	2.9	°C/W
ψ_JB	Junction-to-board characterization parameter	34.9	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	TYP⁽²⁾	MAX	UNIT
V_IK	Input Clamp Voltage	V_CC = 3 V, I_I = –18 mA		–1.2	V
I_IN	Control inputs	V_CC = 4.3 V or 0 V, V_IN = 0 to 4.3 V		±1	µA
I_OZ⁽³⁾		V_CC = 4.3 V, V_O = 0 to 3.6 V, V_I = 0, switch OFF		±1	µA
I_OFF	D+ and D–	V_CC = 0 V, V_O = 0 V to 4.3 V, V_I = 0, V_IN = V_CC or GND		±2	µA
I_CC		V_CC = 4.3 V, I_I/O = 0, switch ON or OFF		1	µA
ΔI_CC⁽⁴⁾	Control inputs	V_CC = 4.3 V, V_IN = 2.6 V		10	µA
C_in	Control inputs	V_CC = 0 V, V_IN = V_CC or GND	1		pF
C_io(OFF)	Off-state input-output capacitance	V_CC = 2.5 V, V_I/O = 2.5 V or 0, switch OFF	2		pF
C_io(OFF)	Off-state input-output capacitance	V_CC = 3.3 V, V_I/O = 3.3 V or 0, switch OFF	2		pF
C_io(ON)	On-state input-output capacitance	V_CC = 2.5 V, V_I/O = 2.5 V or 0, switch ON	6		pF
C_io(ON)	On-state input-output capacitance	V_CC = 3.3 V, V_I/O = 3.3 V or 0, switch ON	6		pF
r_on⁽⁵⁾	On-state resistance	V_CC = 2.5 V, V_I = 0.4 V, I_O = –8 mA	7.5	9	Ω
r_on⁽⁵⁾	On-state resistance	V_CC = 3 V, V_I = 0.4 V, I_O = –8 mA	6.5	10	Ω
Δr_on	Channel match	V_CC = 2.5 V, V_I = 0.4 V, I_O = –8 mA	0.4		Ω
Δr_on	Channel match	V_CC = 3 V, V_I = 0.4 V, I_O = –8 mA	0.35		Ω
r_on(flat)	On-state resistance flatness	V_CC = 2.5 V, V_I = 0 V or 1 V, I_O = –8 mA	0.07		Ω
r_on(flat)	On-state resistance flatness	V_CC = 3 V, V_I = 0 V or 1 V, I_O = –8 mA	2		Ω

(1) V_IN and I_IN refer to control inputs. V_I, V_O, I_I, and I_O refer to data pins.

(2) All typical values are at V_CC = 3.3 V (unless otherwise noted), T_A = 25°C.

(3) For I/O ports, the parameter I_OZ includes the input leakage current.

(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V_CC or GND.

(5) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals.

6.6 Dynamic Electrical Characteristics

over operating range, T_A = –40°C to +85°C, GND = 0 V

PARAMETER		TEST CONDITIONS	TYP⁽¹⁾	UNIT
V_CC = 2.5 V ± 10%
X_TALK	Crosstalk	R_L = 50 Ω, f = 240 MHz, See Figure 6	–53	dB
O_IRR	OFF isolation	R_L = 50 Ω, f = 240 MHz, See Figure 5	–30	dB
BW	Bandwidth (–3 dB)	R_L = 50 Ω, C_L = 5 pF, See Figure 7	1100	MHz
V_CC = 3.3 V ± 10%
X_TALK	Crosstalk	R_L = 50 Ω, f = 240 MHz, See Figure 6	–53	dB
O_IRR	OFF isolation	R_L = 50 Ω, f = 240 MHz, See Figure 5	–30	dB
BW	Bandwidth (–3 dB)	R_L = 50 Ω, C_L = 5 pF, See Figure 7	1100	MHz

(1) For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.

6.7 Switching Characteristics

over operating range, T_A = –40°C to 85°C, GND = 0 V

PARAMETER		TEST CONDITIONS	TYP⁽¹⁾	MAX	UNIT
V_CC = 2.5 V ± 10%
t_pd	Propagation delay⁽²⁾⁽³⁾	R_L = 50 Ω, C_L = 5 pF, See Figure 8	0.25		ns
t_ON	Line enable time, OE to D, nD	R_L = 50 Ω, C_L = 5 pF, See Figure 4		30	ns
t_OFF	Line disable time, OE to D, nD	R_L = 50 Ω, C_L = 5 pF, See Figure 4		25	ns
t_SK(O)	Output skew between centre port to any other port⁽²⁾	R_L = 50 Ω, C_L = 5 pF, See Figure 9	50		ps
t_SK(P)	Skew between opposite transitions of the same output (t_PHL – t_PLH)⁽²⁾	R_L = 50 Ω, C_L = 5 pF, See Figure 9	20		ps
t_J	Total jitter⁽²⁾	R_L = 50 Ω, C_L = 5 pF, t_R = t_F = 500 ps at 480 Mbps (PRBS = 2¹⁵ – 1)	200		ps
V_CC = 3.3 V ± 10%
t_pd	Propagation delay⁽²⁾⁽³⁾	R_L = 50 Ω, C_L = 5 pF, See Figure 8	0.25		ns
t_ON	Line enable time, OE to D, nD	R_L = 50 Ω, C_L = 5 pF, See Figure 4		30	ns
t_OFF	Line disable time, OE to D, nD	R_L = 50 Ω, C_L = 5 pF, See Figure 4		25	ns
t_SK(O)	Output skew between centre port to any other port⁽²⁾	R_L = 50 Ω, C_L = 5 pF, See Figure 9	50		ps
t_SK(P)	Skew between opposite transitions of the same output (t_PHL – t_PLH)⁽²⁾	R_L = 50 Ω, C_L = 5 pF, See Figure 9	20		ps
t_J	Total jitter⁽²⁾	R_L = 50 Ω, C_L = 5 pF, t_R = t_F = 500 ps at 480 Mbps (PRBS = 2¹⁵ – 1)	200		ps

(1) For Max or Min conditions, use the appropriate value specified under Electrical Characteristics for the applicable device type.

(2) Specified by design

(3) The bus switch contributes no propagational delay other than the RC delay of the on resistance of the switch and the load capacitance. The time constant for the switch alone is of the order of 0.25 ns for 10-pF load. Since this time constant is much smaller than the rise and fall times of typical driving signals, it adds very little propagational delay to the system. Propagational delay of the bus switch, when used in a system, is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven side.