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ZHCSN72 june 2023 TPSI2072-Q1

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

DWQ|11
- MPSS144A

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購信息

zhcsn72_oa

6.9 Electrical Characteristics

Unless otherwise noted, all minimum/maximum specifications are over recommended operating conditions. All typical values are measured at T_J = 25°C, V_VDD = 5 V, V_EN1,EN2 = 5 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
PRIMARY SIDE SUPPLY (VDD)
V_{UVLO_R}	VDD undervoltage threshold rising	VDD rising	4	4.2	4.4	V
V_{UVLO_F}	VDD undervoltage threshold falling	VDD falling	3.9	4.1	4.3	V
V_{UVLO_HYS}	VDD undervoltage threshold hysteresis		40	100	150	mV
I_{VDD_ON_S}	VDD current, single channel powered on	V_EN1 = 5 V, V_EN2 = 0 V OR V_EN₁ = 0 V, V_EN2 = 5 V, T_J = 25°C		5	6	mA
I_{VDD_ON_S}	VDD current, single channel powered on	V_EN1 = 5 V, V_EN2 = 0 V OR V_EN₁ = 0 V, V_EN2 = 5 V, –40°C ≤ T_J ≤ 150°C		5	6.5	mA
I_{VDD_ON}	VDD current, both channels powered on	V_EN1,EN2 = 5 V, T_J = 25°C		9	11	mA
I_{VDD_ON}	VDD current, both channels powered on	V_EN1,EN2 = 5 V, –40°C ≤ T_J ≤ 150°C		9	12	mA
I_{VDD_OFF}	VDD current, 5 V, device powered off	V_VDD = 5 V, V_EN1,EN2 = 0 V, T_J = 25°C		3.5	8	μA
		V_VDD = 5 V, V_EN1,EN2 = 0 V, T_J = 105°C		4.5	11	μA
		V_VDD = 5 V, V_EN1,EN2 = 0 V, T_J = 125°C		5.2	16	μA
		V_VDD = 5 V, V_EN1,EN2 = 0 V, –40°C ≤ T_J ≤ 150°C			30	μA
	VDD current, 20 V, device powered off	V_VDD = 20 V, V_EN1,EN2 = 0 V, T_J = 25°C		8	10.5	μA
		V_VDD = 20 V, V_EN1,EN2 = 0 V, T_J = 105°C		10	17
		V_VDD = 20 V, V_EN1,EN2 = 0 V, T_J = 125°C		11	25
		V_VDD = 20 V, V_EN1,EN2 = 0 V, –40°C ≤ T_J ≤ 150°C			40
FET CHARACTERISTICS (S1, S2, SM)
R_DSON	On resistance, S1-SM or SM-S2	I_S1,S2 = 2 mA, T_J = 25°C		65	90	Ω
		I_S1,S2 = 2 mA, T_J = 85°C		88	120
		I_S1,S2 = 2 mA, T_J = 105°C		96	125
		I_S1,S2 = 2 mA, T_J = 125°C		105	140
		I_S1,S2 = 2 mA, –40°C ≤ T_J ≤ 150°C			150
I_OFF	Off leakage, S1-SM or SM-S2, 500 V	V = +/–500 V, T_J = 25°C		.02	0.1	μA
		V = +/–500 V, T_J = 85°C			0.3
		V = +/–500 V, T_J = 105°C			1
		V = +/–500 V, T_J = 125°C			4
		V = +/–500 V, –40°C ≤ T_J ≤ 150°C			20
	Off leakage, S1-SM or SM-S2, 600 V	V = +/–600 V, T_J = 25°C		.02	0.1	μA
		V = +/–600 V, T_J = 85°C			0.5
		V = +/–600 V, T_J = 105°C			1.5
		V = +/–600 V, T_J = 125°C			6
		V = +/–600 V, –40°C ≤ T_J ≤ 150°C			50
V_AVA	Avalanche voltage	I_O = 10 μA, T_J = 25°C	650	770		V
V_AVA	Avalanche voltage	I_O = 100 μA, T_J = 150°C	650	770		V
C_OSS	S1, S2 capacitance	V_S1,S2,SM = 0 V, F = 1 MHz		150		pF
C_{OSS_SM}	SM capacitance	V_SM,S1,S2 = 0 V, F = 1 MHz		300		pF
LOGIC-LEVEL INPUT (EN1, EN2)
V_IL	Input logic low voltage		0.0		0.8	V
V_IH	Input logic high voltage		2.1		20.0	V
V_HYS	Input logic hysteresis		100	250	300	mV
I_IL	Input logic low current	V_EN1,EN2 = 0 V	–1		1	μA
I_IL	Input logic low current	V_EN1,EN2 = 0.8 V	2	4	6.5	μA
I_IH	Input logic high current	V_EN1,EN2 = 5 V	10	25	50	μA
I_IH	Input logic high current	V_EN1,EN2 = 20 V	100	175	350	μA
I_{VDD_FS}	VDD fail-safe current	V_EN1,EN2 = 20 V, V_VDD = 0 V	–0.1	0	0.1	μA
R_PD	Pulldown resistance	Two point measurement, V_EN1,EN2 = 0.5 V and V_EN1,EN2 = 0.8 V	100	200	350	kΩ
NOISE IMMUNITY
CMTI	Common-mode transient immunity	\|V_CM\| = 1000 V			100.0	V/ns