ZHCSN52D April 2010 – December 2023 TPS74701-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| VREF | Internal reference (Adj.) | TA = +25°C | 0.796 | 0.8 | 0.804 | V | ||
| VOUT | Output voltage range | VIN = 5 V, IOUT = 0.5 A | VREF | 3.6 | V | |||
| Accuracy(1) | 2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 0.5 A (Legacy Chip) | –2 | ±0.5 | 2 | % | |||
| 2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 0.5 A (New Chip) | –1.25 | ±0.3 | 1.25 | |||||
| ΔVOUT(ΔVIN) | Line regulation | VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V (Legacy Chip) | 0.03 | %/V | ||||
| VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V (New Chip) | 0.001 | |||||||
| ΔVOUT(ΔIOUT) | Load regulation | 50 mA ≤ IOUT ≤ 0.5 A (Legacy Chip) | 0.09 | %/A | ||||
| 50 mA ≤ IOUT ≤ 0.5 A (New Chip) | 0.11 | |||||||
| VDO | VIN dropout voltage(2) | IOUT = 0.5 A, VBIAS – VOUT(nom) ≥ 1.62 V (Legacy Chip)(3) | 50 | 120 | mV | |||
| IOUT = 0.5 A, VBIAS – VOUT(nom) ≥ 1.62 V (New Chip)(3) | 20 | 40 | ||||||
| VBIAS dropout voltage(2) | IOUT = 0.5 A, VIN = VBIAS (Legacy Chip) | 1.31 | 1.39 | V | ||||
| IOUT = 0.5 A, VIN = VBIAS (New Chip) | 1.1 | 1.3 | ||||||
| ICL | Output current limit | VOUT = 80% × VOUT(nom) (Legacy Chip) | 800 | 1350 | mA | |||
| VOUT = 80% × VOUT(nom) (New Chip) | 800 | 1350 | ||||||
| IBIAS | BIAS pin current | (Legacy Chip) | 1 | 2 | mA | |||
| (New Chip) | 1 | 1.2 | ||||||
| ISHDN | Shutdown supply current (IGND) | VEN ≤ 0.4 V (Legacy Chip) | 1 | 50 | μA | |||
| VEN ≤ 0.4 V (New Chip) | 1 | 10 | ||||||
| IFB | Feedback pin current | (Legacy Chip) | –1 | 0.15 | 1 | μA | ||
| (New Chip) | –30 | 0.15 | 30 | nA | ||||
| PSRR | Power-supply rejection (VIN to VOUT) | 1 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) | 60 | dB | ||||
| 1 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) | 76 | |||||||
| 300 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) | 30 | |||||||
| 300 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (New CHip) | 50 | |||||||
| Power-supply rejection (VBIAS to VOUT) | 1 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) | 50 | ||||||
| 1 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) | 59 | |||||||
| 300 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) | 30 | |||||||
| 300 kHz, IOUT = 0.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) | 49 | |||||||
| Vn | Output noise voltage | BW = 100 Hz to 100 kHz, IOUT = 0.5 A, CSS = 1 nF (Legacy Device) | 25 × VOUT | μVrms | ||||
| BW = 100 Hz to 100 kHz, IOUT = 0.5 A, CSS = 1 nF (New Chip) | 20 × VOUT | |||||||
| tSTR | Minimum startup time | RLOAD for IOUT = 0.5 A, CSS = open (Legacy Device) | 200 | μs | ||||
| RLOAD for IOUT = 0.5 A, CSS = open (New Chip) | 250 | |||||||
| ISS | Soft-start charging current | VSS = 0.4 V (Legacy Chip) | 440 | nA | ||||
| VSS = 0.4 V (New Chip) | 530 | |||||||
| VEN(hi) | Enable input high level | 1.1 | 5.5 | V | ||||
| VEN(lo) | Enable input low level | 0 | 0.4 | V | ||||
| VEN(hys) | Enable pin hysteresis | (Legacy Chip) | 50 | mV | ||||
| (New Chip) | 55 | |||||||
| VEN(dg) | Enable pin deglitch time | 20 | μs | |||||
| IEN | Enable pin current | VEN = 5 V (Legacy Chip) | 0.1 | 1 | μA | |||
| VEN = 5 V (New Chip) | 0.1 | 0.3 | ||||||
| VIT | PG trip threshold | VOUT decreasing | 85 | 90 | 94 | %VOUT | ||
| VHYS | PG trip hysteresis | 3 | %VOUT | |||||
| VPG(lo) | PG output low voltage | IPG = 1 mA (sinking), VOUT < VIT (Legacy Chip) | 0.3 | V | ||||
| IPG = 1 mA (sinking), VOUT < VIT (New Chip) | 0.125 | |||||||
| IPG(lkg) | PG leakage current | VPG = 5.25 V, VOUT > VIT (Legacy Chip) | 0.1 | 1 | μA | |||
| VPG = 5.25 V, VOUT > VIT (New Chip) | 0.1 | 0.05 | ||||||
| TSD | Thermal shutdown temperature | Shutdown, temperature increasing | 165 | ℃ | ||||
| Reset, temperature decreasing | 140 | |||||||