ZHCSNX8B December 2020 – September 2023 TPS6593-Q1
PRODUCTION DATA
The TPS6593-Q1 device contains a SYNCCLKIN (GPIO10) input to synchronize switching clock of the BUCK regulator with the external clock. The block diagram of the clocking and PLL module is shown in Figure 8-8. The external clock is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2 MHz, or 4.4 MHz. The external SYNCCLKIN clock must be inside accuracy limits (–18%/+18%) of the typical input frequency for valid clock detection.
The EXT_CLK_INT interrupt is generated in case the external clock is expected (SEL_EXT_CLK = 1), but it is not available or the clock frequency is not within the valid range.
The TPS6593-Q1 device can also generate a clock signal, SYNCCLKOUT, for external device use. The SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Note: SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output frequency selection can cause glitches on the clock output. The SYNCCLKOUT is available through GPIO8, GPIO9, or GPIO10.