The TPS6593-Q1 device is a Power-Management Integrated Circuit (PMIC), available in a 56-pin, 0.5-mm pitch, 8-mm × 8-mm QFN package. The TPS6593-Q1 is designed for powering embedded systems or System on Chip (SoC) in automotive or industrial applications. The TPS6593-Q1 provides five configurable BUCK regulators, of which four rails have the ability to combine outputs in multi-phase mode. BUCK4 has the ability to supply up to 4 A output current in single-phase mode, while BUCK1, BUCK2, and BUCK3 have the ability to supply up to 3.5 A output current in single-phase mode. When working in multi-phase mode, each BUCK1, BUCK2, BUCK3, and BUCK4 can supply up to 3.5 A output current per phase, adding up to 14 A output current in four-phase configuration. BUCK5 is a single-phase only BUCK regulator, which supports up to 2 A output current. All five of the BUCK regulators have the capability to sink a current up to 1 A, and support dynamic voltage scaling. Double-buffered voltage scaling registers enable each BUCK regulator to transition to a different voltage during operation by SPI or I²C. A digital PLL enables the BUCK regulators to synchronize to an external clock input, with phase delays between the output rails.

The TPS6593-Q1 device also provides three LDO rails, which can supply up to 500 mA output current per rail and can be configured in bypass mode and used as a load switch. One additional low-noise LDO rail can supply up to 300 mA output current. The 500-mA LDOs support 0.6 V to 3.3 V output voltage with 50-mV step. The 300-mA low-noise LDO supports 1.2 V to 3.3 V output voltage with 25-mV step. The output voltages of the LDOs can be pre-configured through the SPI or I²C interfaces, which are used to configure the power rails and the power states of the TPS6593-Q1 device.

I²C channel 1 (I2C1) is the main channel with access to the registers, which control the configurable power sequencer, the states and the outputs of power rails, the device operating states, the RTC registers and the Error Signal Monitors. I²C channel 2 (I2C2), which is available through the GPIO1 and GPIO2 pins, is dedicated for accessing the Q&A Watchdog communication registers. If GPIO1 and GPIO2 are not configured as I2C2 pins, I2C1 can access all of the registers, including the Q&A Watchdog registers. Alternatively, depending on the NVM-configuration of the orderable part number, SPI is the selected interface for the device and can be used to access all registers.

The TPS6593-Q1 device includes an internal RC-oscillator to sequence all resources during power up and power down. Two internal LDOs (LDOVINT and LDOVRTC) generate the supply for the entire digital circuitry of the device as soon as the external input supply is available through the VCCA input. A backup battery supply input can also be used to power the RTC block and a 32-kHz Crystal Oscillator clock generator in the event of main supply power loss.

TPS6593-Q1 device has eleven GPIO pins each with multiple functions and configurable features. All of the GPIO pins, when configured as general-purpose output pins, can be included in the power-up and power-down sequence and used as enable signals for external resources. In addition, each GPIO can be configured as a wake-up input or a sleep-mode trigger. The default configuration of the GPIO pins comes from the non-volatile memory (NVM), and can be re-programmed by system software if the external connection permits.

The TPS6593-Q1 device includes a watchdog with selectable trigger or Q&A modes to monitor MCU software lockup, and two error signal monitor (ESM) inputs with fault injection options to monitor the lock-step signal of the attached SoC or MCU. TPS6593-Q1 includes protection and diagnostic mechanisms such as voltage monitoring on the input supply, voltage monitoring on all BUCK and LDO regulator outputs, CRC on configuration registers, CRC on non-volatile memory, CRC on communication interfaces, current-limit and short-circuit protection on all output rails, thermal pre-warning, and over-temperature shutdown. The device also includes a Q&A or trigger mode watchdog to monitor for MCU software lockup, and two Error Signal Monitor inputs with selectable level mode or PWM mode, and with fault injection options to monitor the error signals from the attached SoC or MCU. The TPS6593-Q1 can notify the processor of these events through the interrupt handler, allowing the MCU to take action in response.