| INPUT SUPPLY |
| VIN |
Input voltage range |
VIN1 and VIN2 |
4.5 |
|
18 |
V |
| IDDSDN |
Shutdown supply current |
EN1 = EN2 = low |
|
10 |
|
µA |
| IDDQ_NSW |
Switching quiescent current with no load at DCDC output |
EN1 = EN2 = 3.3 V With power skip mode, without bucks switching |
|
1.2 |
|
mA |
| IDDQ_SW |
Switching quiescent current with no load at DCDC output, Buck switching |
EN1 = EN2 = 3.3 V With bucks switching |
|
10 |
|
mA |
| UVLO |
VIN undervoltage lockout |
Rising VIN |
|
4.25 |
4.50 |
V |
| Falling VIN |
3.4 |
3.75 |
|
| Hysteresis |
|
0.5 |
|
| V7V |
6.3 V LDO |
V7V load current = 0 A |
6.10 |
6.3 |
6.5 |
V |
| IOCP_V7V |
Current limit of V7V LDO |
|
|
200 |
|
mA |
| ENABLE |
| VENR |
Enable threshold |
Rising |
|
1.21 |
1.3 |
V |
| VENF |
Enable threshold |
Falling |
1.0 |
1.17 |
|
V |
| IENR |
Enable Input current |
EN = 1 V |
|
3 |
|
µA |
| IENF |
Enable hysteresis current |
EN = 1.5 V |
|
3 |
|
µA |
| OSCILLATOR |
| FSW |
Switching frequency |
|
200 |
|
1600 |
kHz |
| ROSC = 100 kΩ (1%) |
340 |
400 |
460 |
| tSYNC_w |
Clock sync minimum pulse width |
|
|
20 |
|
ns |
| VSYNC_HI |
Clock sync high threshold |
|
|
|
2 |
V |
| VSYNC_LO |
Clock sync low threshold |
|
0.8 |
|
|
V |
| VSYNC_D |
Clock falling edge to LX rising edge delay |
|
|
66 |
|
ns |
| FSYNC |
Clock sync frequency range |
|
200 |
|
1600 |
kHz |
| BUCK 1, BUCK 2 CONVERTERS |
| Vref(min) |
Voltage reference |
0 A < IOUT1 < 6 A, 0 A < IOUT2 < 3.5 A |
0.594 |
0.6 |
0.606 |
V |
| VLINEREG |
Line regulation-DC |
IOUT = 2 A |
|
0.5 |
|
%/V |
| VLOADREG |
Load regulation-DC |
IOUT = (10-90%) x IOUT_max |
|
0.5 |
|
%/A |
| Gm_EA |
Error amplifier trans-conductance |
-2 µA < ICOMP < 2 µA |
|
1350 |
|
µS |
| Gm_SRC |
COMP voltage to inductor current Gm |
ILX = 0.5 A |
|
10 |
|
A/V |
| ISSx |
Soft-start pin charging current |
|
|
6 |
|
µA |
| ILIMIT1 |
Buck 1 peak inductor current limit |
RLIM1 = 60.4 kΩ |
|
7.3 |
|
A |
| ILIMIT2 |
Buck 2 peak inductor current limit |
RLIM2 = 60.4 kΩ |
|
7.3 |
|
A |
| ILIMITLSx |
Low side sinking current limit |
|
|
-2.6 |
|
A |
| Rdsonx_HS |
On resistance of high side FET |
V7V = 6.3 V |
|
31 |
|
mΩ |
| Rdsonx_LS |
On resistance of low side FET |
VIN = 12 V |
|
23 |
|
mΩ |
| Tminon |
Minimum on time |
|
|
94 |
|
ns |
| VbootUV |
Boot-LX UVLO |
|
|
2.1 |
3 |
V |
| Thiccupwait |
Hiccup wait time |
|
|
512 |
|
cycles |
| Thiccup_re |
Hiccup time before re-start |
|
|
16384 |
|
cycles |
| PGOOD |
| VPGOOD |
PGOOD trip levels |
FB rising to PGOOD high |
|
94% |
|
|
| FB falling to PGOOD low |
|
92.5% |
|
| FB rising to PGOOD low |
|
107.5% |
|
| FB falliong to PGOOD high |
|
105.5% |
|
| THERMAL SHUTDOWN |
| TTRIP |
Thermal protection trip point |
Rising temperature |
|
160 |
|
°C |
| THYST |
Thermal protection hysteresis |
|
|
20 |
|
°C |