ZHCSG38A March 2017 – November 2022 TPS65263-1Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INPUT SUPPLY VOLTAGE | ||||||
| VIN | Input voltage range | 4 | 18 | V | ||
| UVLO | VIN UVLO | VIN rising | 3.5 | 3.8 | 4 | V |
| VIN falling | 3.1 | 3.3 | 3.5 | V | ||
| Hysteresis | 500 | mV | ||||
| IDDSDN | Shutdown supply current | EN1 = EN2 = EN3 = 0 V | 4 | 9.5 | 18 | μA |
| IDDQ_NSW | Input quiescent current without buck1/2/3 switching | EN1 = EN2 = EN3 = 5 V, FB1 = FB2 = FB3 = 0.8 V | 500 | 750 | 1150 | μA |
| IDDQ_NSW1 | EN1 = 5 V, EN2 = EN3 = 0 V, FB1 = 0.8 V | 180 | 370 | 590 | μA | |
| IDDQ_NSW2 | EN2 = 5 V, EN1 = EN3 = 0 V, FB2 = 0.8V | 180 | 370 | 590 | μA | |
| IDDQ_NSW3 | EN3 = 5 V, EN1 = EN2 = 0 V, FB3 = 0.8 V | 180 | 370 | 590 | μA | |
| V7V | V7V LDO output voltage | V7V load current = 0 A | 6.3 | V | ||
| IOCP_V7V | V7V LDO current limit | 78 | 185 | 260 | mA | |
| FEEDBACK VOLTAGE REFERENCE | ||||||
| VFB | Feedback voltage | VCOMP = 1.2 V | 0.594 | 0.6 | 0.606 | V |
| BUCK1, BUCK2, BUCK3 | ||||||
| VENXH | EN1/2/3 high-level input voltage | 1.12 | 1.2 | 1.26 | V | |
| VENXL | EN1/2/3 low-level input voltage | 1.05 | 1.15 | 1.21 | V | |
| IENX1 | EN1/2/3 pullup current | ENx = 1 V | 2.5 | 3.9 | 5.9 | μA |
| IENX2 | EN1/2/3 pullup current | ENx = 1.5 V | 5.1 | 6.9 | 9.2 | μA |
| IENhys | Hysteresis current | 2.6 | 3 | 3.3 | μA | |
| ISSX | Soft-start charging current | 3.9 | 5.2 | 6.5 | μA | |
| tON_MIN | Minimum on-time | 50 | 75 | 110 | ns | |
| Gm_EA | Error amplifier transconductance | –2 μA < ICOMPX < 2 μA | 140 | 300 | 450 | μs |
| Gm_PS1/2/3 | COMP1/2/3 voltage to inductor current Gm(1) | ILX = 0.5 A | 7.4 | A/V | ||
| ILIMIT1 | Buck1 peak inductor current limit | 4.3 | 5.8 | 6.9 | A | |
| ILIMITSINK1 | Buck1 low-side sink current limit | 0.7 | 1.3 | 1.8 | A | |
| ILIMIT2/3 | Buck2/buck3 peak inductor current limit | 2.55 | 3.4 | 4.1 | A | |
| ILIMITSINK2/3 | Buck2/buck3 low-side sink current limit | 0.5 | 1 | 1.4 | A | |
| Rds(on)_HS1 | Buck1 high-side switch resistance | VIN = 12 V | 105 | mΩ | ||
| Rds(on)_LS1 | Buck1 low-side switch resistance | VIN = 12 V | 65 | mΩ | ||
| Rds(on)_HS2 | Buck2 high-side switch resistance | VIN = 12 V | 140 | mΩ | ||
| Rds(on)_LS2 | Buck2 low-side switch resistance | VIN = 12 V | 90 | mΩ | ||
| Rds(on)_HS3 | Buck3 high-side switch resistance | VIN = 12 V | 140 | mΩ | ||
| Rds(on)_LS3 | Buck3 low-side switch resistance | VIN = 12 V | 90 | mΩ | ||
| HICCUP TIMING | ||||||
| tHiccup_wait | Overcurrent wait time(1) | 256 | cycles | |||
| tHiccup_re | Hiccup time before restart(1) | 8192 | cycles | |||
| POWER GOOD | ||||||
| Vth_PG | Feedback voltage threshold | FBx undervoltage falling | 92.5 | %VREF | ||
| FBx undervoltage rising | 95 | |||||
| FBx overvoltage rising | 107.5 | |||||
| FBx overvoltage falling | 105 | |||||
| tDEGLITCH(PG)_F | PGOOD falling edge deglitch time | 112 | cycles | |||
| tRDEGLITCH(PG)_R | PGOOD rising edge deglitch time | 616 | cycles | |||
| IPG | PGOOD pin leakage | 0.1 | μA | |||
| VLOW_PG | PGOOD pin low voltage | ISINK = 1 mA | 0.4 | V | ||
| OSCILLATOR | ||||||
| FSW | Switching frequency | ROSC = 88.7 kΩ | 430 | 500 | 560 | kHz |
| FSW_range | Switching frequency | 200 | 2300 | kHz | ||
| TSYNC_w | Clock sync minimum pulse width | 80 | ns | |||
| FSYNC_HI | Clock sync high threshold | 2 | V | |||
| VSYNC_LO | Clock sync low threshold | 0.4 | V | |||
| FSYNC | Clock sync frequency range | 200 | 2300 | kHz | ||
| THERMAL PROTECTION | ||||||
| TTRIP_OTP | Thermal protection trip point(1) | Temperature rising | 160 | °C | ||
| THYST_OTP | Hysteresis | 20 | °C | |||
| I2C INTERFACE | ||||||
| Addr | Address(2) | 0x60H | ||||
| VIH SDA,SCL | Input high voltage | 2 | V | |||
| VIL SDA,SCL | Input low voltage | 0.4 | V | |||
| II | Input current | SDA, SCL, VI = 0.4 to 4.5 V | –10 | 10 | μA | |
| VOL SDA | SDA output low voltage | SDA open drain, IOL = 4 mA | 0.4 | V | ||
| ?(SCL) | Maximum SCL clock frequency(2) | 400 | kHz | |||
| tBUF | Bus free time between a STOP and START condition(2) | 1.3 | μs | |||
| tHD_STA | Hold time (repeated) START condition(2) | 0.6 | μs | |||
| tSU_STO | Setup time for STOP condition(2) | 0.6 | μs | |||
| tLOW | Low period of the SCL clock(2) | 1.3 | μs | |||
| tHIGH | High period of the SCL clock(2) | 0.6 | μs | |||
| tSU_STA | Setup time for a repeated START condition(2) | 0.6 | μs | |||
| tSU_DAT | Data setup time(2) | 0.1 | μs | |||
| tHD_DAT | Data hold time(2) | 0 | 0.9 | μs | ||
| tRCL | Rise time of SCL signal(2) | Capacitance of one bus line (pF) | 20 + 0.1CB | 300 | ns | |
| tRCL1 | Rise time of SCL signal after a repeated START condition and after an acknowledge bit(2) | Capacitance of one bus line (pF) | 20 + 0.1CB | 300 | ns | |
| tFCL | Fall time of SCL signal(2) | Capacitance of one bus line (pF) | 20 + 0.1CB | 300 | ns | |
| tRDA | Rise time of SDA signal(2) | Capacitance of one bus line (pF) | 20 + 0.1CB | 300 | ns | |
| tFDA | Fall time of SDA signal(2) | Capacitance of one bus line (pF) | 20 + 0.1CB | 300 | ns | |
| CB | Capacitance of bus line(SCL and SDA)(2) | 400 | pF | |||