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ZHCSG38A March 2017 – November 2022 TPS65263-1Q1

PRODUCTION DATA

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

RHB|32
- MPQF130D

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

RHB|32
- QFND029X

訂購信息

6.5 Electrical Characteristics

V_IN = 12 V, F_SW = 500 kHz, T_J = –40°C to 125°C, typical values are at T_J = 25°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY VOLTAGE
VIN	Input voltage range		4		18	V
UVLO	VIN UVLO	VIN rising	3.5	3.8	4	V
		VIN falling	3.1	3.3	3.5	V
		Hysteresis		500		mV
IDD_SDN	Shutdown supply current	EN1 = EN2 = EN3 = 0 V	4	9.5	18	μA
IDD_{Q_NSW}	Input quiescent current without buck1/2/3 switching	EN1 = EN2 = EN3 = 5 V, FB1 = FB2 = FB3 = 0.8 V	500	750	1150	μA
IDD_{Q_NSW1}		EN1 = 5 V, EN2 = EN3 = 0 V, FB1 = 0.8 V	180	370	590	μA
IDD_{Q_NSW2}		EN2 = 5 V, EN1 = EN3 = 0 V, FB2 = 0.8V	180	370	590	μA
IDD_{Q_NSW3}		EN3 = 5 V, EN1 = EN2 = 0 V, FB3 = 0.8 V	180	370	590	μA
V_7V	V7V LDO output voltage	V_7V load current = 0 A		6.3		V
I_{OCP_V7V}	V7V LDO current limit		78	185	260	mA
FEEDBACK VOLTAGE REFERENCE
V_FB	Feedback voltage	V_COMP = 1.2 V	0.594	0.6	0.606	V
BUCK1, BUCK2, BUCK3
V_ENXH	EN1/2/3 high-level input voltage		1.12	1.2	1.26	V
V_ENXL	EN1/2/3 low-level input voltage		1.05	1.15	1.21	V
I_ENX1	EN1/2/3 pullup current	ENx = 1 V	2.5	3.9	5.9	μA
I_ENX2	EN1/2/3 pullup current	ENx = 1.5 V	5.1	6.9	9.2	μA
I_ENhys	Hysteresis current		2.6	3	3.3	μA
I_SSX	Soft-start charging current		3.9	5.2	6.5	μA
t_{ON_MIN}	Minimum on-time		50	75	110	ns
G_{m_EA}	Error amplifier transconductance	–2 μA < I_COMPX < 2 μA	140	300	450	μs
G_{m_PS1/2/3}	COMP1/2/3 voltage to inductor current G_m⁽¹⁾	I_LX = 0.5 A		7.4		A/V
I_LIMIT1	Buck1 peak inductor current limit		4.3	5.8	6.9	A
I_LIMITSINK1	Buck1 low-side sink current limit		0.7	1.3	1.8	A
I_LIMIT2/3	Buck2/buck3 peak inductor current limit		2.55	3.4	4.1	A
I_LIMITSINK2/3	Buck2/buck3 low-side sink current limit		0.5	1	1.4	A
R_{ds(on)_HS1}	Buck1 high-side switch resistance	V_IN = 12 V		105		mΩ
R_{ds(on)_LS1}	Buck1 low-side switch resistance	V_IN = 12 V		65		mΩ
R_{ds(on)_HS2}	Buck2 high-side switch resistance	V_IN = 12 V		140		mΩ
R_{ds(on)_LS2}	Buck2 low-side switch resistance	V_IN = 12 V		90		mΩ
R_{ds(on)_HS3}	Buck3 high-side switch resistance	V_IN = 12 V		140		mΩ
R_{ds(on)_LS3}	Buck3 low-side switch resistance	V_IN = 12 V		90		mΩ
HICCUP TIMING
t_{Hiccup_wait}	Overcurrent wait time⁽¹⁾			256		cycles
t_{Hiccup_re}	Hiccup time before restart⁽¹⁾			8192		cycles
POWER GOOD
V_{th_PG}	Feedback voltage threshold	FBx undervoltage falling		92.5		%V_REF
		FBx undervoltage rising		95
		FBx overvoltage rising		107.5
		FBx overvoltage falling		105
t_{DEGLITCH(PG)_F}	PGOOD falling edge deglitch time			112		cycles
t_{RDEGLITCH(PG)_R}	PGOOD rising edge deglitch time			616		cycles
I_PG	PGOOD pin leakage				0.1	μA
V_{LOW_PG}	PGOOD pin low voltage	I_SINK = 1 mA			0.4	V
OSCILLATOR
F_SW	Switching frequency	R_OSC = 88.7 kΩ	430	500	560	kHz
F_{SW_range}	Switching frequency		200		2300	kHz
T_{SYNC_w}	Clock sync minimum pulse width		80			ns
F_{SYNC_HI}	Clock sync high threshold				2	V
V_{SYNC_LO}	Clock sync low threshold		0.4			V
F_SYNC	Clock sync frequency range		200		2300	kHz
THERMAL PROTECTION
T_{TRIP_OTP}	Thermal protection trip point⁽¹⁾	Temperature rising		160		°C
T_{HYST_OTP}	Thermal protection trip point⁽¹⁾	Hysteresis		20		°C
I²C INTERFACE
Addr	Address⁽²⁾	0x60H
V_IH SDA,SCL	Input high voltage				2	V
V_IL SDA,SCL	Input low voltage		0.4			V
I_I	Input current	SDA, SCL, VI = 0.4 to 4.5 V	–10		10	μA
VOL SDA	SDA output low voltage	SDA open drain, I_OL = 4 mA			0.4	V
?_(SCL)	Maximum SCL clock frequency⁽²⁾		400			kHz
t_BUF	Bus free time between a STOP and START condition⁽²⁾		1.3			μs
t_{HD_STA}	Hold time (repeated) START condition⁽²⁾		0.6			μs
t_{SU_STO}	Setup time for STOP condition⁽²⁾		0.6			μs
t_LOW	Low period of the SCL clock⁽²⁾		1.3			μs
t_HIGH	High period of the SCL clock⁽²⁾		0.6			μs
t_{SU_STA}	Setup time for a repeated START condition⁽²⁾		0.6			μs
t_{SU_DAT}	Data setup time⁽²⁾		0.1			μs
t_{HD_DAT}	Data hold time⁽²⁾		0		0.9	μs
t_RCL	Rise time of SCL signal⁽²⁾	Capacitance of one bus line (pF)	20 + 0.1CB		300	ns
t_RCL1	Rise time of SCL signal after a repeated START condition and after an acknowledge bit⁽²⁾	Capacitance of one bus line (pF)	20 + 0.1CB		300	ns
t_FCL	Fall time of SCL signal⁽²⁾	Capacitance of one bus line (pF)	20 + 0.1CB		300	ns
t_RDA	Rise time of SDA signal⁽²⁾	Capacitance of one bus line (pF)	20 + 0.1CB		300	ns
t_FDA	Fall time of SDA signal⁽²⁾	Capacitance of one bus line (pF)	20 + 0.1CB		300	ns
C_B	Capacitance of bus line(SCL and SDA)⁽²⁾				400	pF

(1) Lab validation result

(2) Not production tested