ZHCSED1A November 2015 – November 2015 TPS53317A
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購(gòu)信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGB|20
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RGB|20
訂購(gòu)信息
5 Pin Configuration and Functions
RGB Package
20-Pin VFQN
Top View
Pin Functions
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| BST | 16 | I | Power supply for internal high-side gate driver. Connect a 0.1-µF bootstrap capacitor between this pin and the SW pin. Include a series boot resistor when the voltage spike on switching node is above 7 V. |
| COMP | 8 | O | Connect an R-C-C network between this pin and VREF for loop compensation. |
| EN | 17 | I | Enable pin (3.3-V logic compatible). |
| GND | 6 | – | Analog ground. |
| MODE | 18 | I | Allows selection of different operation modes. (See Table 1) |
| PGND | 1 | G | Power ground. |
| 2 | |||
| 3 | |||
| PGOOD | 19 | O | Open drain power good output. Connect pullup resistor. |
| REFIN | 9 | I | External tracking reference input. Apply voltage between 0.45 V to 2.0 V. For non-tracking mode, connect REFIN to VREF via resistor divider. |
| SW | 11 | I/O | Switching node output. |
| 12 | |||
| 13 | |||
| 14 | |||
| 15 | |||
| V5IN | 20 | I | 5-V power supply for analog circuits and gate drive. |
| VIN | 4 | I | Power supply input pin. |
| 5 | |||
| VOUT | 10 | I | Output voltage monitor input pin. |
| VREF | 7 | O | 2.0-V reference output. Connect a ceramic capacitor with a value of 0.22-µF or greater between this pin and GND. |
(1) I = Input, O = Output, G = Ground