SLUSA41B JUNE 2010 – September 2016 TPS53311
PRODUCTION DATA.
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | EN | I | Enable. Internally pulled up to VDD with a 1.35-MΩ resistor. |
| 2 | SYNC | B | Synchronization signal for input interleaving. Master SYNC pin sends out 180° out-of-phase signal to slave SYNC. SYNC frequency must be within ±20% of slave nominal frequency. |
| 3 | PGD | O | Power good output flag. Open drain output. Pull up to an external rail through a resistor. |
| 4 | VBST | P | Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW terminal. |
| 5 | SW | B | Output inductor connection to integrated power devices. |
| 6 | SW | B | Output inductor connection to integrated power devices. |
| 7 | SW | B | Output inductor connection to integrated power devices. |
| 8 | PS | I | Mode configuration pin (with 10 µA current): Connecting to ground: Forced CCM slave. Pulled high or floating (internal pulled high): Forced CCM master. Connect with 24.3 kΩ to GND: DE slave. Connect with 57.6 kΩ to GND: HEF mode. Connect with 105 kΩ to GND: reserved mode. Connect with 174 kΩ to GND: DE master. |
| 9 | COMP | O | Error amplifier compensation terminal. Type III compensation method is recommended for stability. |
| 10 | FB | I | Voltage feedback. Also used for OVP, UVP, and PGD determination. |
| 11 | AGND | G | Device analog ground terminal. |
| 12 | VDD | P | Input bias supply for analog functions. |
| 13 | VIN | P | Gate driver supply and power conversion voltage. |
| 14 | VIN | P | Gate driver supply and power conversion voltage. |
| 15 | PGND | P | IC power GND terminal. |
| 16 | PGND | P | IC power GND terminal. |