ZHCSHX8D September 2017 – October 2019 TPS50601A-SP
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 VIN and Power VIN Pins (VIN and PVIN)
- 7.3.2 Voltage Reference
- 7.3.3 Adjusting the Output Voltage
- 7.3.4 Safe Start-Up Into Prebiased Outputs
- 7.3.5 Error Amplifier
- 7.3.6 Slope Compensation
- 7.3.7 Enable and Adjust UVLO
- 7.3.8 Adjustable Switching Frequency and Synchronization (SYNC)
- 7.3.9 Slow Start (SS/TR)
- 7.3.10 Power Good (PWRGD)
- 7.3.11 Sequencing (SS/TR)
- 7.3.12 Output Overvoltage Protection (OVP)
- 7.3.13 Overcurrent Protection
- 7.3.14 Thermal Shutdown
- 7.3.15 Turn-On Behavior
- 7.3.16 Small Signal Model for Frequency Compensation
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機械、封裝和可訂購信息
7.3.3 Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output (VOUT) to the VSENSE pin. TI recommends to use 1% tolerance or better resistors. Start with a 10 kΩ for RTOP and use Equation 1 to calculate RBOTTOM. To improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is more susceptible to noise and voltage errors from the VSENSE input current are noticeable.
Equation 1. 
where
- VREF = 0.804 V