ZHCSIV9F September 2009 – October 2018 TPS386000 , TPS386040
PRODUCTION DATA.
This design is intended to monitor the voltage rails for an FPGA. Table 7 summarizes the design requirements.
| PARAMETER | DESIGN REQUIREMENT |
|---|---|
| VDD | 5 V |
| VMON(1) | 1.8 V –5% |
| VMON(2) | 1.5 V –5% |
| VMON(3) | 1.2 V –5% |
| VMON(4) | 1 V ±5% |
| Approximate start-up time | 100 ms |