ZHCSMY9C January 2021 – December 2024 TMUX6219-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Thermal Information
- 5.4 Recommended Operating Conditions
- 5.5 Source or Drain Continuous Current
- 5.6 ±15 V Dual Supply: Electrical Characteristics?
- 5.7 ±15 V Dual Supply: Switching Characteristics?
- 5.8 36 V Single Supply: Electrical Characteristics?
- 5.9 36 V Single Supply: Switching Characteristics?
- 5.10 12 V Single Supply: Electrical Characteristics?
- 5.11 12 V Single Supply: Switching Characteristics?
- 5.12 +5 V / -8 V Dual Supply: Electrical Characteristics?
- 5.13 +5 V / -8 V?Dual Supply: Switching Characteristics?
- 5.14 ±5 V Dual Supply: Electrical Characteristics?
- 5.15 ±5 V Dual Supply: Switching Characteristics?
- 5.16 Typical Characteristics
-
6 Parameter Measurement Information
- 6.1 On-Resistance
- 6.2 Off-Leakage Current
- 6.3 On-Leakage Current
- 6.4 Transition Time
- 6.5 tON(EN) and tOFF(EN)
- 6.6 Break-Before-Make
- 6.7 tON (VDD) Time
- 6.8 Propagation Delay
- 6.9 Charge Injection
- 6.10 Off Isolation
- 6.11 Crosstalk
- 6.12 Bandwidth
- 6.13 THD + Noise
- 6.14 Power Supply Rejection Ratio (PSRR)
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- DGK|8
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
7.3.6 Ultra-Low Charge Injection
The TMUX6219-Q1 has a transmission gate topology, as shown in Figure 7-2. Any mismatch in the stray capacitance associated with the NMOS and PMOS causes an output level change whenever the switch is opened or closed.
Figure 7-2 Transmission Gate TopologyThe TMUX6219-Q1 contains specialized architecture to reduce charge injection on the source (Sx). To further reduce charge injection in a sensitive application, a compensation capacitor (Cp) can be added on the drain (D). This will ensure that excess charge from the switch transition will be pushed into the compensation capacitor on the drain (D) instead of the source (Sx). As a general rule, Cp should be 20× larger than the equivalent load capacitance on the source (Sx). Figure 7-3 shows charge injection variation with source voltage with different compensation capacitors on the Drain side.
Figure 7-3 Charge Injection Compensation