ZHCSKJ6 December   2019 TL16C750E

PRODUCTION DATA.  

1. 1 特性
2. 2 應(yīng)用
3. 3 說(shuō)明
   1.     方框圖
4. 4 修訂歷史記錄
5. 5 說(shuō)明 （續(xù)）
6. 6 Pin Configuration and Functions
   1.     Pin Functions
7. 7 Specifications
   1. Table 1. Absolute Maximum Ratings
   2. 7.1      ESD Ratings
   3. Table 2. Recommended Operating Conditions
   4. Table 3. Thermal Information
   5. Table 4. Electrical Characteristics
   6. Table 5. Timing Requirements
   7. 7.2      Typical Characteristics
8. 8 Parameter Measurement Information
9. 9 Detailed Description
   1. 9.1 Overview
   2. 9.2 Functional Block Diagrams
   3. 9.3 Feature Description
      1. 9.3.1  UART Modes
      2. 9.3.2  Trigger Levels
      3. 9.3.3  Hardware Flow Control
      4. 9.3.4  Auto-RTS
      5. 9.3.5  Auto-CTS
      6. 9.3.6  Software Flow Control
      7. 9.3.7  Software Flow Control Example
      8. 9.3.8  Reset
      9. 9.3.9  Interrupts
      10. 9.3.10 Interrupt Mode Operation
      11. 9.3.11 Polled Mode Operation
      12. 9.3.12 Break and Timeout Conditions
      13. 9.3.13 Programmable Baud Rate Generator with Fractional Divisor
      14. 9.3.14 Fractional Divisor
   4. 9.4 Device Functional Modes
      1. 9.4.1 Device Interface Mode
         1. 9.4.1.1 IOR Used (MODE = VCC)
         2. 9.4.1.2 IOR Unused (MODE = GND)
      2. 9.4.2 DMA Signaling
         1. 9.4.2.1 Single DMA Transfers (DMA Mode 0 or FIFO Disable)
         2. 9.4.2.2 Block DMA Transfers (DMA Mode 1)
      3. 9.4.3 Sleep Mode
   5. 9.5 Register Maps
      1. 9.5.1  Registers Operations
      2. 9.5.2  Receiver Holding Register (RHR)
      3. 9.5.3  Transmit Holding Register (THR)
      4. 9.5.4  FIFO Control Register (FCR)
      5. 9.5.5  Line Control Register (LCR)
      6. 9.5.6  Line Status Register (LSR)
      7. 9.5.7  Modem Control Register (MCR)
      8. 9.5.8  Modem Status Register (MSR)
      9. 9.5.9  Interrupt Enable Register (IER)
      10. 9.5.10 Interrupt Identification Register (IIR)
      11. 9.5.11 Enhanced Feature Register (EFR)
      12. 9.5.12 Divisor Latches (DLL, DLH, DLF)
      13. 9.5.13 Transmission Control Register (TCR)
      14. 9.5.14 Trigger Level Register (TLR)
      15. 9.5.15 FIFO Ready Register
      16. 9.5.16 Alternate Function Register (AFR)
      17. 9.5.17 RS-485 Mode
      18. 9.5.18 IrDA Overview
      19. 9.5.19 IrDA Encoder Function
10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
       1. 10.2.1 Design Requirements
       2. 10.2.2 Detailed Design Procedure
          1. 10.2.2.1 Set the desired baud rate
          2. 10.2.2.2 Reset the fifos
          3. 10.2.2.3 Sending data on the bus
       3. 10.2.3 Application Curves
11. 11Power Supply Recommendations
12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
13. 13器件和文檔支持
    1. 13.1 文檔支持
       1. 13.1.1 相關(guān)文檔
    2. 13.2 接收文檔更新通知
    3. 13.3 支持資源
    4. 13.4 商標(biāo)
    5. 13.5 靜電放電警告
    6. 13.6 Glossary
14. 14機(jī)械、封裝和可訂購(gòu)信息