ZHCSEZ1F April 2016 – June 2024 THS6212
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| AC PERFORMANCE | |||||||
| SSBW | Small-signal bandwidth, –3 dB | AV = 5 V/V, RF = 1.5 kΩ, VO = 2 VPP | 285 | MHz | |||
| AV = 10 V/V, RF = 1.24 kΩ, VO = 2 VPP | 205 | ||||||
| 0.1-dB bandwidth flatness | 13 | MHz | |||||
| LSBW | Large-signal bandwidth | VO = 40 VPP | 170 | MHz | |||
| SR | Slew rate (20% to 80% level) | VO = 40-V step | 11,000 | V/μs | |||
| Rise and fall time | VO = 2 VPP | 2 | ns | ||||
| HD2 | 2nd-order harmonic distortion | AV = 10 V/V, VO = 2 VPP, RL = 100 Ω |
Full bias, f = 1 MHz | –86 | dBc | ||
| Low bias, f = 1 MHz | –79 | ||||||
| Full bias, f = 10 MHz | –71 | ||||||
| Low bias, f = 10 MHz | –63 | ||||||
| HD3 | 3rd-order harmonic distortion | AV = 10 V/V, VO = 2 VPP, RL = 100 Ω |
Full bias, f = 1 MHz | –101 | dBc | ||
| Low bias, f = 1 MHz | –88 | ||||||
| Full bias, f = 10 MHz | –80 | ||||||
| Low bias, f = 10 MHz | –65 | ||||||
| en | Differential input voltage noise | f ≥ 1 MHz, input-referred | 2.5 | nV/√Hz | |||
| in+ | Noninverting input current noise (each amplifier) | f ≥ 1 MHz | 1.7 | pA/√Hz | |||
| in? | Inverting input current noise (each amplifier) | f ≥ 1 MHz | 18 | pA/√Hz | |||
| DC PERFORMANCE | |||||||
| ZOL | Open-loop transimpedance gain | 1500 | kΩ | ||||
| Input offset voltage | ±12 | mV | |||||
| Input offset voltage drift | TA = –40°C to +85°C | –40 | μV/°C | ||||
| Input offset voltage matching | Amplifier A to B | ±0.5 | mV | ||||
| Noninverting input bias current | ±1 | μA | |||||
| Inverting input bias current | ±6 | μA | |||||
| Inverting input bias current matching | ±8 | μA | |||||
| INPUT CHARACTERISTICS | |||||||
| Common-mode input voltage | Each input | ±9 | ±10 | V | |||
| CMRR | Common-mode rejection ratio | Each input | 53 | 65 | dB | ||
| Noninverting input resistance | 10 || 2 | kΩ || pF | |||||
| Inverting input resistance | 38 | Ω | |||||
| OUTPUT CHARACTERISTICS | |||||||
| VO | Output voltage swing(1) | RL = 100 Ω | ±24.5 | V | |||
| RL = 25 Ω | ±12.3 | ||||||
| IO | Output current (sourcing and sinking)(1) | RL = 25 Ω, based on VO specification | ±580 | ±665 | mA | ||
| Short-circuit output current | 1 | A | |||||
| ZO | Output impedance | f = 1 MHz, differential | 0.01 | Ω | |||
| POWER SUPPLY | |||||||
| VS | Operating voltage | 10 | 12 | 28 | V | ||
| TA = –40°C to +85°C | 10 | 28 | |||||
| IS+ | Quiescent current, positive rail, VS+ | Full bias (BIAS-1 = 0, BIAS-2 = 0) | 23 | mA | |||
| Mid bias (BIAS-1 = 1, BIAS-2 = 0) | 17.5 | ||||||
| Low bias (BIAS-1 = 0, BIAS-2 = 1) | 11.9 | ||||||
| Bias off (BIAS-1 = 1, BIAS-2 = 1) | 1.1 | 1.3 | |||||
| IS– | Quiescent current, negative rail, VS? | Full bias (BIAS-1 = 0, BIAS-2 = 0) | 22 | mA | |||
| Mid bias (BIAS-1 = 1, BIAS-2 = 0) | 16.4 | ||||||
| Low bias (BIAS-1 = 0, BIAS-2 = 1) | 10.8 | ||||||
| Bias off (BIAS-1 = 1, BIAS-2 = 1) | 0.1 | 0.8 | |||||
| Current through GND pin | Full bias (BIAS-1 = 0, BIAS-2 = 0) | 1 | mA | ||||
| +PSRR | Positive power-supply rejection ratio | Differential | 83 | dB | |||
| –PSRR | Negative power-supply rejection ratio | Differential | 77 | dB | |||
| BIAS CONTROL | |||||||
| Bias control pin voltage | With respect to GND pin, TA = –40°C to +85°C |
0 | 3.3 | 14.5 | V | ||
| Bias control pin logic threshold | Logic 1, with respect to GND pin, TA = –40°C to +85°C |
1.9 | V | ||||
| Logic 0, with respect to GND pin, TA = –40°C to +85°C |
0.8 | ||||||
| Bias control pin current(2) | BIAS-1, BIAS-2 = 0.5 V (logic 0) | –15 | –10 | μA | |||
| BIAS-1, BIAS-2 = 3.3 V (logic 1) | 0.1 | 1 | |||||