ZHCSF24 May 2016 TDC7201
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3 Feature Description
- 7.4 Device Functional Modes
- 7.5 Programming
- 7.6
Register Maps
- 7.6.1 Register Initialization
- 7.6.2 TDCx_CONFIG1: TDCx Configuration Register 1 R/W (address = 00h, CSBx asserted) [reset = 0h]
- 7.6.3 TDCx_CONFIG2: TDCx Configuration Register 2 R/W (address = 01h, CSBx asserted) [reset = 40h]
- 7.6.4 TDCx_INT_STATUS: Interrupt Status Register (address = 02h, CSBx asserted) [reset = 00h]
- 7.6.5 TDCx_INT_MASK: TDCx Interrupt Mask Register R/W (address = 03h, CSBx asserted) [reset = 07h]
- 7.6.6 TDCx_COARSE_CNTR_OVF_H: Coarse Counter Overflow High Value Register (address = 04h, CSBx asserted) [reset = FFh]
- 7.6.7 TDCx_COARSE_CNTR_OVF_L: TDCx Coarse Counter Overflow Low Value Register (address = 05h, CSBx asserted) [reset = FFh ]
- 7.6.8 TDCx_CLOCK_CNTR_OVF_H: Clock Counter Overflow High Register (address = 06h, CSBx asserted) [reset = FFh]
- 7.6.9 TDCx_CLOCK_CNTR_OVF_L: Clock Counter Overflow Low Register (address = 07h, CSBx asserted) [reset = FFh]
- 7.6.10 TDCx_CLOCK_CNTR_STOP_MASK_H: CLOCK Counter STOP Mask High Value Register (address = 08h, CSBx asserted) [reset = 00h]
- 7.6.11 TDCx_CLOCK_CNTR_STOP_MASK_L: CLOCK Counter STOP Mask Low Value Register (address = 09h, CSBx asserted) [reset = 00h]
- 7.6.12 TDCx_TIME1: Time 1 Register (address: 10h, CSBx asserted) [reset = 00_0000h]
- 7.6.13 TDCx_CLOCK_COUNT1: Clock Count Register (address: 11h, CSBx asserted) [reset = 00_0000h]
- 7.6.14 TDCx_TIME2: Time 2 Register (address: 12h, CSBx asserted) [reset = 00_0000h]
- 7.6.15 TDCx_CLOCK_COUNT2: Clock Count Register (address: 13h, CSBx asserted) [reset = 00_0000h]
- 7.6.16 TDCx_TIME3: Time 3 Register (address: 14h, CSBx asserted) [reset = 00_0000h]
- 7.6.17 TDCx_CLOCK_COUNT3: Clock Count Registers (address: 15h, CSBx asserted) [reset = 00_0000h]
- 7.6.18 TDCx_TIME4: Time 4 Register (address: 16h, CSBx asserted) [reset = 00_0000h]
- 7.6.19 TDCx_CLOCK_COUNT4: Clock Count Register (address: 17h, CSBx asserted) [reset = 00_0000h]
- 7.6.20 TDCx_TIME5: Time 5 Register (address: 18h, CSBx asserted) [reset = 00_0000h]
- 7.6.21 TDCx_CLOCK_COUNT5: Clock Count Register (address: 19h, CSBx asserted) [reset = 00_0000h]
- 7.6.22 TDCx_TIME6: Time 6 Register (address: 1Ah, CSBx asserted) [reset = 00_0000h]
- 7.6.23 TDCx_CALIBRATION1: Calibration 1 Register (address: 1Bh, CSBx asserted) [reset = 00_0000h]
- 7.6.24 TDCx_CALIBRATION2: Calibration 2 Register (address: 1Ch, CSBx asserted) [reset = 00_0000h]
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
7 Detailed Description
7.1 Overview
The TDC7201 has two built-in TDCs with the capability to simultaneously and individually measure time delay on two pairs of START and STOP pins. Each TDC is a stopwatch that measures time between a single event (edge on START pin) and multiple subsequent events (edge on STOP pin). An event from a START pulse to a STOP pulse is also known as time-of-flight, or TOF for short. The TDC has an internal time base that is used to measure time with accuracy in the order of picoseconds. This accuracy makes the TDC7201 ideal for applications such as drones and range finders, which require high accuracy in the picoseconds range.
NOTE
In rest of the documentation, we use TDCx to refer each TDC of the TDC7201, where x = 1, 2. Also, the prefix TDCx is used in register names to identify the TDC the register belongs to. Further the associated START, STOP, TRIGG, CSB, DOUT, and INTB pins of TDCx are represented as STARTx, STOPx, TRIGGx, CSBx, DOUTx, and INTBx.
7.2 Functional Block Diagram
NOTE
Do not tie together VREG1 and VREG2.
7.3 Feature Description
7.3.1 LDO
The LDO (low-dropout) is an internal supply voltage regulator for the TDC7201. Each of the two TDC cores of the TDC7201 has its own dedicated LDO. No external circuitry needs to be connected to the output of this regulator other than the mandatory external decoupling capacitor on VREG1 and VREG2.
Recommendations for the decoupling capacitor parameters:
- Type: ceramic
- Capacitance: 0.4 µF to 2.7 µF (1 µF typical). If using a capacitor value outside the recommended range, the part may malfunction and can be damaged.
- ESR: 100 mΩ (maximum)
7.3.2 CLOCK
The TDC7201 needs an external reference clock connected to the CLOCK pin. This external clock input serves as the reference clock for both TDCs of the TDC7201. The external CLOCK is used to calibrate the internal time base accurately and therefore, the measurement accuracy is heavily dependent on the external CLOCK accuracy. This reference clock is also used by all digital circuits inside the device; thus, CLOCK has to be available and stable at all times when the device is enabled (ENABLE = HIGH).
Figure 20 shows the typical effect of the external CLOCK frequency on the measurement uncertainty. With a reference clock of 1 MHz, the standard deviation of a set of measurement results is approximately 243 ps. As the reference clock frequency is increased, the standard deviation (or measurement uncertainty) reduces. Therefore, using a reference clock of 16 MHz is recommended for optimal performance.
Figure 20. Standard Deviation vs CLOCK
7.3.3 Counters
7.3.3.1 Coarse and Clock Counters Description
Time measurements by each TDCx of the TDC7201 rely on two counters: the Coarse Counter and the Clock Counter. The Coarse Counter counts the number of times the ring oscillator (the TDCx’s core time measurement mechanism) wraps, which is used to generate the results in the TDCx_TIME1 to TDCx_TIME6 registers.
The Clock Counter counts the number of integer clock cycles between START and STOP events and is used in Measurement Mode 2 only. The results for the Clock Counter are displayed in the TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5 registers.
7.3.3.2 Coarse and Clock Counters Overflow
Once the coarse counter value has reached the corresponding value of the Coarse Counter Overflow registers, then its interrupt bit will be set to 1. In other words, if (TDCx_TIMEn / 63) ≥ COARSE_CNTR_OVF, then COARSE_CNTR_OVF_INT = 1 (this interrupt bit is located in the TDCx_INT_STATUS register).
TDCx_COARSE_CNTR_OVF = (TDCx_COARSE_CNTR_OVF_H x 28 + TDCx_COARSE_CNTR_OVF_L), where TDCx_TIMEn refers to the TDCx_TIME1 to TDCx_TIME6 registers.
Similarly, once the clock counter value has reached the corresponding value of the Clock Counter Overflow registers, then its interrupt bit will be set to 1. In other words, if TDCx_CLOCK_COUNTn > TDCx_CLOCK_CNTR_OVF, then CLOCK_CNTR_OVF_INT = 1 (this interrupt bit is located in the INT_STATUS register).
TDCx_CLOCK_CNTR_OVF = (TDCx_CLOCK_CNTR_OVF_H × 28 + TDCx_CLOCK_CNTR_OVF_L), where TDCx_CLOCK_COUNTn refers to the TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5 registers.
As soon as there is an overflow detected, the running measurement will be terminated immediately.
7.3.3.3 Clock Counter STOP Mask
The values in the Clock Counter STOP Mask registers define the end of the mask window. The Clock Counter STOP Mask value will be referred to as TDCx_CLOCK_CNTR_STOP_MASK = (TDCx_CLOCK_CNTR_STOP_MASK_H x 28 + TDCx_CLOCK_CNTR_STOP_MASK_L).
The Clock Counter is started by the first rising edge of the external CLOCK after the START signal (see Figure 23). All STOP signals occurring before the value set by the TDCx_CLOCK_CNTR_STOP_MASK registers will be ignored. This feature can be used to help suppress wrong or unwanted STOP trigger signals.
For example, assume the following values:
- The first time-of-flight (TOF1), which is defined as the time measurement from the START to the 1st STOP = 19 μs.
- The second time-of-flight (TOF2), which is defined as the time measurement from the START to the 2nd STOP = 119 μs.
- CLOCK = 8 MHz
In this example, the TDC7201 will provide a TDCx_CLOCK_COUNT1 of approximately 152 (19 μs / tCLOCK), and TDCx_CLOCK_COUNT2 of approximately 952 (119 μs / tCLOCK). If the user sets TDCx_CLOCK_CNTR_STOP_MASK anywhere between 152 and 952, then the 1st STOP will be ignored and 2nd STOP will be measured.
The Clock Counter Overflow value (TDCx_CLOCK_CNTR_OVF_H × 28 + TDCx_CLOCK_CNTR_OVF_L) should always be higher than the Clock Counter STOP Mask value (TDCx_CLOCK_CNTR_STOP_MASK_H × 28 + TDCx_CLOCK_CNTR_STOP_MASK_L). Otherwise, the Clock Counter Overflow Interrupt will be set before the STOP mask time expires, and the measurement will be halted.
7.3.3.4 ENABLE
The ENABLE pin is used as a reset to all digital circuits in the TDC7201. Therefore, it is essential that the ENABLE pin sees a positive edge after the device has powered up. It is also important to ensure that there are no transients (such as glitches) on the ENABLE pin; such glitches could cause the device to reset
7.4 Device Functional Modes
7.4.1 Calibration
The time measurements performed by each TDCx of the TDC7201 are based on an internal time base which is represented as the LSB value of the TDCx_TIME1 to TDCx_TIME6 results registers. The typical LSB value can be seen in Electrical Characteristics. However, the actual value of the LSB can vary depending on environmental variables (temperature, systematic noise, and so forth). This variation can introduce significant error into the measurement result. There is also an offset error in the measurement due to certain internal delays in the device.
In order to compensate for these errors and to calculate the actual LSB value, calibration needs to be performed. The TDCx calibration consists of two measurement cycles of the external CLOCK. The first is a measurement of a single clock cycle period of the external clock; the second measurement is for the number of external CLOCK periods set by the CALIBRATION2_PERIODS in the TDCx_CONFIG2 register. The results from the calibration measurements are stored in the TDCx_CALIBRATION1 and TDCx_CALIBRATION2 registers.
The two-point calibration is used to determine the actual LSB in real time in order to convert the TDCx_TIME1 to TDCx_TIME6 results from number of delays to a real TOF number. Calibration is automatic and performed every time after a measurement and before measurement completion interrupt is sent to the MCU through INTBx pin. Only if a measurement is interrupted (for example, due to counter overflow or missing STOP signal), calibration is not performed. As discussed in the next sections, the calibrations will be used for calculating TOF in measurement modes 1 and 2.
7.4.2 Measurement Modes
7.4.2.1 Measurement Mode 1
In measurement mode 1, as shown in Figure 21, each TDCx of the TDC7201 performs the entire counting from START to the last STOP using its internal ring oscillator plus coarse counter. This method is recommended for measuring shorter time durations of < 2000 ns. TI does not recommend using measurement mode 1 for measuring time > 2000 ns because this decreases accuracy of the measurement (as shown in Figure 22).
Figure 21. Measurement Mode 1
Figure 22. Measurement Mode 1 Standard Deviation vs Measured Time-of-Flight
7.4.2.1.1 Calculating Time-of-Flight (Measurement Mode 1)
For measurement mode 1, the TOF between the START to the nth STOP can be calculated using Equation 1:
where
- TOFn [sec] = time-of-flight measurement from the START to the nth STOP
- TIMEn = nth TIME measurement given by the TIME1 to TIME6 registers
- normLSB [sec] = normalized LSB value from calibration
- CLOCKperiod [sec] = external CLOCK period
- CALIBRATION1 = TDCx_CALIBRATION1 register value = TDC count for first calibration cycle
- CALIBRATION2 = TDCx_CALIBRATION2 register value = TDC count for second calibration cycle
- CALIBRATION2_PERIODS = setting for the second calibration cycle; located in register TDCx_CONFIG2
For example, assume the time-of-flight between the START to the 1st STOP is desired, and the following readouts were obtained:
- TDCx_CALIBRATION2 = 21121 (decimal)
- TDCx_CALIBRATION1 = 2110 (decimal)
- CALIBRATION2_PERIODS = 10
- CLOCK = 8 MHz
- TDCx_TIME1 = 4175 (decimal)
Therefore, the calculation for time-of-flight is:
- calCount = (21121 – 2110) / (10 – 1) = 2112.33
- normLSB = (1/8MHz) / (2112.33) = 59.17 ps
- TOF1 = (4175)(5.917 x 10-11) = 247.061 ns
7.4.2.2 Measurement Mode 2
In measurement mode 2, the internal ring oscillator of each TDCx of the TDC7201 is used only to count fractional parts of the total measured time. As shown in Figure 23, the internal ring oscillator starts counting from when it receives the START signal until the first rising edge of the CLOCK. Then, the internal ring oscillator switches off, and the Clock counter starts counting the clock cycles of the external CLOCK input until a STOP pulse is received. The internal ring oscillator again starts counting from the STOP signal until the next rising edge of the CLOCK.
Figure 23. Measurement Mode 2
7.4.2.2.1 Calculating Time-of-Flight (TOF) (Measurement Mode 2)
The TOF between the START to the nth STOP can be calculated using Equation 2:
where
- TOFn [sec] = time-of-flight measurement from the START to the nth STOP
- TIME1 = TDCx_TIME1 register value = time 1 measurement given by the TDC7201 register address 0x10
- TIME(n+1) = TDCx_TIME(n+1) register value = (n+1) time measurement, where n = 1 to 5 (TDCx_TIME2 to TDCx_TIME6 registers)
- normLSB [sec] = normalized LSB value from calibration
- CLOCK_COUNTn = nth clock count, where n = 1 to 5 (TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5)
- CLOCKperiod [sec] = external CLOCK period
- CALIBRATION1 = TDCx_CALIBRATION1 register value = TDC count for first calibration cycle
- CALIBRATION2 = TDCx_CALIBRATION2 register value = TDC count for second calibration cycle
- CALIBRATION2_PERIODS = setting for the second calibration; located in register TDCx_CONFIG2
For example, assume the time-of-flight between the START to the 1st STOP is desired, and the following readouts were obtained:
- CALIBRATION2 = 23133 (decimal)
- CALIBRATION1 = 2315 (decimal)
- CALIBRATION2_PERIODS = 10
- CLOCK = 8 MHz
- TIME1 = 2147 (decimal)
- TIME2 = 201 (decimal)
- CLOCK_COUNT1 = 318 (decimal)
Therefore, the calculation for time-of-flight is:
7.4.3 Timeout
For one STOP, each TDCx of the TDC7201 performs the measurement by counting from the START signal to the STOP signal. If no STOP signal is received, either the Clock Counter or Coarse Counter will overflow and will generate an interrupt (see Coarse and Clock Counters Overflow). If no START signal is received, the timer waits indefinitely for a START signal to arrive.
For multiple STOPs, each TDCx performs the measurement by counting from the START signal to the last STOP signal. All earlier STOP signals are captured and stored into the corresponding Measurement Results registers (TDCx_TIME1 to TDCx_TIME6, TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5, TDCx_CALIBRATION1, TDCx_CALIBRATION2). The minimum time required between two consecutive STOP signals is defined in the Recommended Operating Conditions table. The device can be programmed to measure up to 5 STOP signals by setting the NUM_STOP bits in the TDCx_CONFIG2 register.
7.4.4 Multi-Cycle Averaging
In the Multi-Cycle Averaging Mode, the TDC7201 will perform a series of measurements on its own and will only send an interrupt to the MCU (for example, MSP430, C2000, and so forth) for wake up after the series has been completed. While waiting, the MCU can remain in sleep mode during the whole cycle (as shown in Figure 24).
Multi-Cycle Averaging Mode Setup and Conditions:
- The number of averaging cycles should be selected (1 to 128). This is done by programming the AVG_CYCLES bit in the TDCx_CONFIG2 register.
- The results of all measurements are reported in the Measurement Results registers (TDCx_TIME1 to TDCx_TIME6, TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5, TDCx_CALIBRATION1, TDCx_CALIBRATION2 registers). The CLOCK_COUNTn registers should be right shifted by the log2(AVG_CYCLES) before calculating the TOF. For example, if using the multi-cycle averaging mode, Equation 2 should be rewritten as: TOFn = normLSB [TDCx_TIME1 - TDCx_TIME(n+1)] + [TDCx_CLOCK_COUNTn >> log 2 (AVG_CYCLES)] x [CLOCKperiod]
- Following each average cycle, the TDCx generates either a trigger event on the TRIGGx pin after the calibration measurement to commence a new measurement or an interrupt on the INTBx pin, indicating that the averaging sequence has completed.
This mode allows multiple measurements without MCU interaction, thus optimizing power consumption for the overall system.
Figure 24. Multi-Cycle Averaging Mode Example with 2 Averaging Cycles and 5 STOP Signals
7.4.5 START and STOP Edge Polarity
In order to achieve the highest measurement accuracy, having the same edge polarity for the START and STOP input signals is highly recommended. Otherwise, slightly different propagation delays due to symmetry shift between the rising and falling edge configuration will impact the measurement accuracy.
For highest measurement accuracy in measurement mode 2, TI recommends to choose for the START and STOP signal the rising edge. This is done by setting the START_EDGE and STOP_EDGE bits in the TDCx_CONFIG1 register to 0.
7.4.6 Measurement Sequence
The TDC7201 has two built-in TDCs with the capability to simultaneously and individually measure time delay on two pairs of START and STOP pins. Each TDCx is a stopwatch that measures time between a single event (edge on STARTx pin) and multiple subsequent events (edge on STOPx pin). The measurement sequence for each TDCx is as follows:
- After powering up the device, the ENABLE pin needs to be low. There is one low to high transition required while VDD is supplied for correct initialization of the device.
- MCU software requests new TDCx measurements to be initiated through the SPI™ interface.
- After the start new measurement bit START_MEAS has been set in the TDCx_CONFIG1 register, the TDCx generates a trigger signal on the TRIGGx pin, which is typically used by the corresponding ultrasonic analog-front-end (such as the TDC1000) as start trigger for a measurement (for example, transmit signal for the ultrasonic burst).
- Immediately after sending the trigger, the TDCx enables the STARTx pin and waits to receive the START pulse edge.
- After receiving a START, the TDCx resets the TRIGGx pin.
- The Clock counter is started after the next rising edge of the external clock signal (Measurement Mode 2). The Clock Counter STOP Mask registers (TDCx_CLOCK_CNTR_STOP_MASK_H and TDCx_CLOCK_CNTR_STOP_MASK_L) determine the length of the STOP mask window.
- After reaching the Clock Counter STOP Mask value, the STOPx pin waits to receive a single or multiple STOP trigger signal from the analog-front-end (for example, detected echo signal of the ultrasonic burst signal).
- After the last STOP trigger has been received, the TDCx will signal to the MCU through interrupt (INTBx pin) that there are new measurement results waiting in the registers. STARTx, STOPx and TRIGGx pins are disabled (in Multi-Cycle Averaging Mode, the TDCx will start the next cycle automatically by generating a new TRIGG signal). INTBx goes back to high whenever a new measurement is initiated through SPI or when the TDCx_INT_STATUS register bit NEW_MEAS_INT is cleared by writing a 1 to it.
- After the results are retrieved, the MCU can then start a new measurement with the same register settings. This is done by just setting the START_MEAS bit through SPI. It is not required to drive the ENABLE pin low between measurements.
- The ENABLE pin can be taken low, if the time duration between measurements is long, and it is desired to put the TDC7201 in its lowest power state. However, upon taking ENABLE high again, the device will come up with its default register settings and will need to be configured through SPI.
NOTE
Pins VDD1 and VDD2 must be tied together at the board level and supplied from the same source.
NOTE
INTBx must be utilized to determine TDCx measurement completion; polling the TDCx_INT_STATUS register to determine measurement completion is NOT recommended as it will interfere with the TDCx measurement.
The two TDCs of TDC7201 can be used independently to measure TOF. When used independently, the TDCx operation is as explained in the measurement sequence steps above. In this case, each TDCx has dedicated START, STOP inputs and measures their STARTx to STOPx time individually when the START_MEAS bit in the TDCx_CONFIG1 register is set. The MCU has to set up, control, and read the results from the two TDCs individually through the master SPI interface. To set up the registers and read back measurement results of TDCx, MCU needs to perform SPI read and write transactions with corresponding CSBx asserted.
NOTE
START1, STOP1 and START2, STOP2 inputs can be separate from different sources or can be identical with START1 connected to START2 and STOP1 connected to STOP2. In the latter case, when the TDCx inputs are connected together and the TDCx register setup is identical, then both the TDCs measure the same input in parallel and this can be used to achieve finer resolution. By measuring the same time with both TDCs and taking the average, the LSB resolution is halved.
7.4.7 Wait Times for TDC7201 Startup
The required wait time following the rising edge of the ENABLE pin of the TDC7201 is defined by three key times, as shown in Figure 25. All three times relate to the startup of the TDCx’s internal dedicated LDO, which is power gated when the device is disabled for optimal power consumption. The first parameter, T1SPI_RDY, is the time after which the SPI interface is accessible. The second (T2LDO_SET1) parameter and third (T3LDO_SET2) parameter are related to the performance of a measurement made while the internal LDO is settling. The LDO supplies the TDC7201’s time measurement device, and a change in voltage on its supply during a measurement translates directly to an inaccuracy. It is therefore recommended to wait until the LDO is settled before time measurement begins.
The first time period relating to the measurement accuracy is T2LDO_SET1, the LDO settling time 1. This is the time after which the LDO has settled to within 0.3% of its final value. A 0.3% error translates to a worst case time error (due to the LDO settling) of 0.3% × tCLOCK, which is 375 ps in the case of an 8-MHz reference clock, or 187.5 ps if a 16-MHz clock is used. Finally, the time T3LDO_SET2 is the time after which the LDO has settled to its final value. For best performance, TI recommends that a time measurement is not started before T3LDO_SET2 to allow the LDO to fully settle. Typical times for these parameters are: T1SPI_RDY is 100 µs, for T2LDO_SET1 is 300 µs, and for T3LDO_SET2 is 1.5 ms.
Figure 25. VREGx Startup Time
7.5 Programming
7.5.1 Serial Peripheral Interface (SPI)
The serial interface consists of data input (DIN), data output (DOUTx), serial interface clock (SCLK), and chip select bar (CSBx). The serial interface is used to configure the TDC7201 parameters available in various configuration registers.
The two TDCs of TDC7201 share the serial interface DIN and SCLK pins but support dedicated CSB and DOUT pins. Registers of the TDCx are selected for read/write access when their corresponding dedicated CSBx pin is asserted. By connecting together DOUT1 and DOUT2, a single SPI master interface of the MCU can be used to access both the TDC register sets by asserting the corresponding CSBx. Alternatively, by keeping DOUT1 and DOUT2 separate, data can be read out of the TDCs in parallel using their dedicated DOUTx pins. This doubles the data readout throughput but requires a second dedicated SPI interface of the MCU.
The communication on the SPI bus supports write and read transactions. A write transaction consists of a single write command byte, followed by single data byte. A read transaction consists of a single read command byte followed by 8 or 24 SCLK cycles. The write and read command bytes consist of a 1-bit auto-increment bit, a 1-bit read or write instruction, and a 6-bit register address. Figure 26 shows the SPI protocol for a transaction involving one byte of data (read or write).
Figure 26. SPI Protocol
7.5.1.1 CSBx
CSBx is an active-low signal and needs to be low throughout a transaction. That is, CSBx should not pulse between the command byte and the data byte of a single transaction.
De-asserting CSBx always terminates an ongoing transaction, even if it is not yet complete. Re-asserting CSBx will always bring the device into a state ready for the next transaction, regardless of the termination status of a previous transaction.
Registers of the TDCx are selected for read/write access when their corresponding dedicated CSBx pin is asserted.
7.5.1.2 SCLK
SPI clock can idle high or low. TI recommends to keep SCLK as clean as possible to prevent glitches from corrupting the SPI frame.
7.5.1.3 DIN
Data In (DIN) is driven by the SPI master by sending the command and the data byte to configure the TDC7201.
7.5.1.4 DOUTx
Data Out (DOUTx) is driven by the TDC7201 when the SPI master initiates a read transaction with CSBx asserted. When the TDC7201 is not being read out, the DOUT pin is in high impedance mode and is undriven.
Registers of the TDCx are selected for read/write access when their corresponding dedicated CSBx pin is asserted. By connecting together DOUT1 and DOUT2, a single SPI master interface of the MCU can be used to access both the TDC register sets by asserting the corresponding CSBx. Alternatively, by keeping DOUT1 and DOUT2 separate, data can be read out of the TDCs in parallel using their dedicated DOUTx pins. This doubles the data readout throughput but requires a second dedicated SPI interface of the MCU.
7.5.1.5 Register Read/Write
Access to the TDCx internal registers can be done through the serial interface formed by pins CSBx (Chip Select - active low), SCLK (serial interface clock), DIN (data input), and DOUTx (data out).
Serial shift of bits into the TDCx is enabled when CSBx is low. Serial data DIN is latched (MSB received first, LSB received last) at every rising edge of SCLK when CSBx is active (low). The serial data is loaded into the register with the last data bit SCLK rising edge when CSBx is low. In the case that the word length exceeds the register size, the excess bits are ignored. The interface can work with SCLK frequency from 25 MHz down to very low speeds (a few Hertz) and even with a non-50% duty-cycle SCLK.
The SPI transaction is divided in two main portions:
- Address and Control as shown in Table 1: Auto Increment Mode selection bit, Read/Write bit, Address 6 bits
- Data: 8 bit or 24 bit
When writing to a register with unused bits, these should be set to 0.
Table 1. Address and Control Byte of SPI transaction
| Address and Control (A7 - A0) | |||||||
|---|---|---|---|---|---|---|---|
| A7 | A6 | A5 | A4 | A3 | A2 | A1 | A0 |
| Auto Increment | RW | Register Address | |||||
| 0: OFF 1: ON |
Read = 0 Write = 1 |
00 h up to 3Fh | |||||
7.5.1.6 Auto Increment Mode
When the Auto Increment Mode is OFF, only the register indicated by the Register Address will be accessed, all cycles beyond the register length will be ignored. When the Auto Increment is ON, the register of the Register Address is accessed first, then without interruption, subsequent registers are accessed.
The Auto Increment Mode can be either used to access the configuration (TDCx_CONFIG1 and TDCx_CONFIG2) and status (TDCx_INT_STATUS) registers, or for the Measurement Results registers (TDCx_TIME1 to TDCx_TIME6, TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5, TDCx_CALIBRATION1, TDCx_CALIBRATION2). As both register block use registers with different length, it is not possible to access all registers of the device within one single access cycle.
7.6 Register Maps
7.6.1 Register Initialization
After power up (VDD supplied, ENABLE Pin low to high transition) the internal registers are initialized with the default value. Disabling the part by pulling ENABLE pin to GND will set the device into total shutdown. As the internal LDO is turned off settings in the register will be lost. The device initializes the registers with default values with the next enable (ENABLE pin to VDD).
Table 2. TDCx_ Register Summary(1)
| REGISTER ADDRESS | REGISTER NAME | REGISTER DESCRIPTION | SIZE (BITS) | RESET VALUE |
|---|---|---|---|---|
| 00h | TDCx_CONFIG1 | Configuration Register 1 | 8 | 00h |
| 01h | TDCx_CONFIG2 | Configuration Register 2 | 8 | 40h |
| 02h | TDCx_INT_STATUS | Interrupt Status Register | 8 | 00h |
| 03h | TDCx_INT_MASK | Interrupt Mask Register | 8 | 07h |
| 04h | TDCx_COARSE_CNTR_OVF_H | Coarse Counter Overflow Value High | 8 | FFh |
| 05h | TDCx_COARSE_CNTR_OVF_L | Coarse Counter Overflow Value Low | 8 | FFh |
| 06h | TDCx_CLOCK_CNTR_OVF_H | CLOCK Counter Overflow Value High | 8 | FFh |
| 07h | TDCx_CLOCK_CNTR_OVF_L | CLOCK Counter Overflow Value Low | 8 | FFh |
| 08h | TDCx_CLOCK_CNTR_STOP_MASK_H | CLOCK Counter STOP Mask High | 8 | 00h |
| 09h | TDCx_CLOCK_CNTR_STOP_MASK_L | CLOCK Counter STOP Mask Low | 8 | 00h |
| 10h | TDCx_TIME1 | Measured Time 1 | 24 | 00_0000h |
| 11h | TDCx_CLOCK_COUNT1 | CLOCK Counter Value | 24 | 00_0000h |
| 12h | TDCx_TIME2 | Measured Time 2 | 24 | 00_0000h |
| 13h | TDCx_CLOCK_COUNT2 | CLOCK Counter Value | 24 | 00_0000h |
| 14h | TDCx_TIME3 | Measured Time 3 | 24 | 00_0000h |
| 15h | TDCx_CLOCK_COUNT3 | CLOCK Counter Value | 24 | 00_0000h |
| 16h | TDCx_TIME4 | Measured Time 4 | 24 | 00_0000h |
| 17h | TDCx_CLOCK_COUNT4 | CLOCK Counter Value | 24 | 00_0000h |
| 18h | TDCx_TIME5 | Measured Time 5 | 24 | 00_0000h |
| 19h | TDCx_CLOCK_COUNT5 | CLOCK Counter Value | 24 | 00_0000h |
| 1Ah | TDCx_TIME6 | Measured Time 6 | 24 | 00_0000h |
| 1Bh | TDCx_CALIBRATION1 | Calibration 1, 1 CLOCK Period | 24 | 00_0000h |
| 1Ch | TDCx_CALIBRATION2 | Calibration 2, 2/10/20/40 CLOCK Periods | 24 | 00_0000h |
7.6.2 TDCx_CONFIG1: TDCx Configuration Register 1 R/W (address = 00h, CSBx asserted) [reset = 0h]
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FORCE_CAL | PARITY_EN | TRIGG_EDGE | STOP_EDGE | START_EDGE | MEAS_MODE | START_MEAS | |
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 3. TDCx_CONFIG1 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | FORCE_CAL | R/W | 0 |
0: Calibration is automatic and performed every time after a measurement. Only if a measurement is interrupted (for example, due to counter overflow or missing STOP signal), calibration is not performed. 1: Calibration is always performed at the end (for example, after a counter overflow) even if a measurement is interrupted. |
| 6 | PARITY_EN | R/W | 0 |
0: Parity bit for Measurement Result Registers* disabled (Parity Bit always 0) 1: Parity bit for Measurement Result Registers enabled (Even Parity) *The Measurement Results registers are the TDCx_TIME1 to TDCx_TIME6, TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5, TDCx_CALIBRATION1, TDCx_CALIBRATION2 registers. |
| 5 | TRIGG_EDGE | R/W | 0 |
0: TRIGG is output as a Rising edge signal 1: TRIGG is output as a Falling edge signal |
| 4 | STOP_EDGE | R/W | 0 |
0: Measurement is stopped on Rising edge of STOP signal 1: Measurement is stopped on Falling edge of STOP signal |
| 3 | START_EDGE | R/W | 0 |
0: Measurement is started on Rising edge of START signal 1: Measurement is started on Falling edge of START signal |
| [2:1] | MEAS_MODE | R/W | b00 | 00: Measurement Mode 1 (for expected time-of-flight < 2000 ns). 01: Measurement Mode 2 (recommended) 10, 11: Reserved for future functionality |
| 0 | START_MEAS | R/W | 0 |
Start New Measurement: 0: No effect 1: Start New Measurement. Writing a 1 will clear all bits in the Interrupt Status Register and Start the measurement (by generating a TRIGG signal) and will reset the content of all Measurement Results registers (TDCx_TIME1 to TDCx_TIME6, TDCx_CLOCK_COUNT1 to TDCx_CLOCK_COUNT5, TDCx_CALIBRATION1, TDCx_CALIBRATION2) to 0. |
7.6.3 TDCx_CONFIG2: TDCx Configuration Register 2 R/W (address = 01h, CSBx asserted) [reset = 40h]
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CALIBRATION2_PERIODS | AVG_CYCLES | NUM_STOP | |||||
| R/W-0 | R/W-1 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 4. TDCx_CONFIG2 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| [7:6] | CALIBRATION2_PERIODS | R/W | b01 |
00: Calibration 2 - measuring 2 CLOCK periods 01: Calibration 2 - measuring 10 CLOCK periods 10: Calibration 2 - measuring 20 CLOCK periods 11: Calibration 2 - measuring 40 CLOCK periods |
| [5:3] | AVG_CYCLES | R/W | b000 |
000: 1 Measurement Cycle only (no Multi-Cycle Averaging Mode) 001: 2 Measurement Cycles 010: 4 Measurement Cycles 011: 8 Measurement Cycles 100: 16 Measurement Cycles 101: 32 Measurement Cycles 110: 64 Measurement Cycles 111: 128 Measurement Cycles |
| [2:0] | NUM_STOP | R/W | b000 |
000: Single Stop 001: Two Stops 010: Three Stops 011: Four Stops 100: Five Stops 101, 110, 111: No Effect. Single Stop |
7.6.4 TDCx_INT_STATUS: Interrupt Status Register (address = 02h, CSBx asserted) [reset = 00h]
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | MEAS_ COMPLETE_ FLAG |
MEAS_STARTED_ FLAG |
CLOCK_ CNTR_ OVF_INT |
COARSE_CNTR_ OVF_INT |
NEW_MEAS_ INT |
||
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 5. TDCx_INT_STATUS Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 - 5 | Reserved | R/W | b000 |
|
| 4 | MEAS_COMPLETE_FLAG | R/W | 0 |
Writing a 1 will clear the status 0: Measurement has not completed 1: Measurement has completed (same information as NEW_MEAS_INT) |
| 3 | MEAS_STARTED_FLAG | R/W | 0 |
Writing a 1 will clear the status 0: Measurement has not started 1: Measurement has started (START signal received) |
| 2 | CLOCK_CNTR_OVF_INT | R/W | 0 |
Requires writing a 1 to clear interrupt status 0: No overflow detected 1: Clock overflow detected, running measurement will be stopped immediately |
| 1 | COARSE_CNTR_OVF_INT | R/W | 0 |
Requires writing a 1 to clear interrupt status 0: No overflow detected 1: Coarse overflow detected, running measurement will be stopped immediately |
| 0 | NEW_MEAS_INT | R/W | 0 |
Requires writing a 1 to clear interrupt status 0: Interrupt not detected 1: Interrupt detected – New Measurement has been completed |
7.6.5 TDCx_INT_MASK: TDCx Interrupt Mask Register R/W (address = 03h, CSBx asserted) [reset = 07h]
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Reserved | CLOCK_CNTR _OVF_MASK |
COARSE_CNTR _OVF_MASK |
NEW_MEAS _MASK |
||||
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-1h | R/W-1h | R/W-1h |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 6. TDCx_INT_MASK Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 - 3 | Reserved | R/W | b0'0000 | |
| 2 | CLOCK_CNTR_OVF_MASK | R/W | 1 |
0: CLOCK Counter Overflow Interrupt disabled 1: CLOCK Counter Overflow Interrupt enabled |
| 1 | COARSE_CNTR_OVF_MASK | R/W | 1 |
0: Coarse Counter Overflow Interrupt disabled 1: Coarse Counter Overflow Interrupt enabled |
| 0 | NEW_MEAS_MASK | R/W | 1 |
0: New Measurement Interrupt disabled 1: New Measurement Interrupt enabled |
A disabled interrupt will no longer be visible on the device pin (INTB). The interrupt bit in the TDCx_INT_STATUS register will still be active.
7.6.6 TDCx_COARSE_CNTR_OVF_H: Coarse Counter Overflow High Value Register (address = 04h, CSBx asserted) [reset = FFh]
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COARSE_CNTR_OVF_H | |||||||
| R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 7. TDCx_COARSE_CNTR_OVF_H Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | COARSE_CNTR_OVF_H | R/W | FFh | Coarse Counter Overflow Value, upper 8 Bit |
7.6.7 TDCx_COARSE_CNTR_OVF_L: TDCx Coarse Counter Overflow Low Value Register (address = 05h, CSBx asserted) [reset = FFh ]
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| COARSE_CNTR_OVF_L | |||||||
| R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 8. TDCx_COARSE_CNTR_OVF_L Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | COARSE_CNTR_OVF_L | R/W | FFh |
Coarse Counter Overflow Value, lower 8 Bit Note: Do not set COARSE_CNTR_OVF_L to 1. |
7.6.8 TDCx_CLOCK_CNTR_OVF_H: Clock Counter Overflow High Register (address = 06h, CSBx asserted) [reset = FFh]
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLOCK_CNTR_OVF_H | |||||||
| R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 9. TDCx_CLOCK_CNTR_OVF_H Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | CLOCK_CNTR_OVF_H | R/W | FFh | CLOCK Counter Overflow Value, upper 8 Bit |
7.6.9 TDCx_CLOCK_CNTR_OVF_L: Clock Counter Overflow Low Register (address = 07h, CSBx asserted) [reset = FFh]
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLOCK_CNTR_OVF_L | |||||||
| R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 | R/W-1 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 10. TDCx_CLOCK_CNTR_OVF_L Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | CLOCK_CNTR_OVF_L | R/W | FFh | CLOCK Counter Overflow Value, lower 8 Bit |
7.6.10 TDCx_CLOCK_CNTR_STOP_MASK_H: CLOCK Counter STOP Mask High Value Register (address = 08h, CSBx asserted) [reset = 00h]
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLOCK_CNTR_STOP_MASK_H | |||||||
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 11. TDCx_CLOCK_CNTR_STOP_MASK_H Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | CLOCK_CNTR_STOP_MASK_H | R/W | 00h | CLOCK Counter STOP Mask, upper 8 Bit |
7.6.11 TDCx_CLOCK_CNTR_STOP_MASK_L: CLOCK Counter STOP Mask Low Value Register (address = 09h, CSBx asserted) [reset = 00h]
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CLOCK_CNTR_STOP_MASK_L | |||||||
| R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 | R/W-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 12. TDCx_CLOCK_CNTR_STOP_MASK_L Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | CLOCK_CNTR_STOP_MASK_L | R/W | 00h | CLOCK Counter STOP Mask, lower 8 Bit |
7.6.12 TDCx_TIME1: Time 1 Register (address: 10h, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | TIME1: 23 bit integer value (Bit 22: MSB, Bit 0: LSB) | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 13. TDCx_TIME1 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity Bit | R | 0 | Parity Bit |
| 22-0 | TIME1 | R | 00 0000h | 23 bits, TIME1 measurement result |
7.6.13 TDCx_CLOCK_COUNT1: Clock Count Register (address: 11h, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | CLOCK_COUNT1 | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 14. TDCx_CLOCK_COUNT1 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity Bit | R | 0 | Parity Bit |
| 22-16 | Not Used | R | 00h | 7 bits, these bits will be used in Multi-Cycle Averaging Mode in order to allow higher averaging results. |
| 15-0 | CLOCK_COUNT1 | R | 0000h | 16 bits, CLOCK_COUNT1 measurement result |
7.6.14 TDCx_TIME2: Time 2 Register (address: 12h, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | TIME2: 23 bit integer value (Bit 22: MSB, Bit 0: LSB) | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 15. TDCx_TIME2 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity Bit | R | 0 | Parity Bit |
| 22-0 | TIME2 | R | 00 0000h | 23 bits, TIME2 measurement result |
7.6.15 TDCx_CLOCK_COUNT2: Clock Count Register (address: 13h, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | CLOCK_COUNT2 | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 16. TDCx_CLOCK_COUNT2 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity bit | R | 0 | Parity Bit |
| 22-16 | Not Used | R | 00h | 7 bits, these bits will be used in Multi-Cycle Averaging Mode in order to allow higher averaging results. |
| 15-0 | CLOCK_COUNT2 | R | 0000h | 16 bits, CLOCK_COUNT2 measurement result |
7.6.16 TDCx_TIME3: Time 3 Register (address: 14h, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | TIME3: 23 bit integer value (Bit 22: MSB, Bit 0: LSB) | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 17. TDCx_TIME3 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity bit | R | 0 | Parity Bit |
| 22-0 | TIME3 | R | 00 0000h | 23 bits, TIME3 measurement result |
7.6.17 TDCx_CLOCK_COUNT3: Clock Count Registers (address: 15h, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | CLOCK_COUNT3 | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 18. TDCx_CLOCK_COUNT3 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity bit | R | 0 | Parity bit |
| 22-16 | Not Used | R | 00h | 7 bits, these bits will be used in Multi-Cycle Averaging Mode in order to allow higher averaging results. |
| 15-0 | CLOCK_COUNT3 | R | 0000h | 16 bits, CLOCK_COUNT3 measurement result |
7.6.18 TDCx_TIME4: Time 4 Register (address: 16h, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | TIME4: 23 bit integer value (Bit 22: MSB, Bit 0: LSB) | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 19. TDCx_TIME4 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity bit | R | 0 | Parity Bit |
| 22-0 | TIME4 | R | 00 0000h | 23 bits, TIME4 measurement result |
7.6.19 TDCx_CLOCK_COUNT4: Clock Count Register (address: 17h, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | CLOCK_COUNT4 | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 20. TDCx_CLOCK_COUNT4 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity bit | R | 0 | Parity bit |
| 22-16 | Not Used | R | 00h | 7 bits, these bits will be used in Multi-Cycle Averaging Mode in order to allow higher averaging results. |
| 15-0 | CLOCK_COUNT4 | R | 0000h | 16 bits, CLOCK_COUNT4 measurement result |
7.6.20 TDCx_TIME5: Time 5 Register (address: 18h, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | TIME5: 23 bit integer value (Bit 22: MSB, Bit 0: LSB) | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 21. TDCx_TIME5 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity bit | R | 0 | Parity Bit |
| 22-0 | TIME5 | R | 00 0000h | 23 bits, TIME5 measurement result |
7.6.21 TDCx_CLOCK_COUNT5: Clock Count Register (address: 19h, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | CLOCK_COUNT5 | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 22. TDCx_CLOCK_COUNT5 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity bit | R | 0 | Parity bit |
| 22-16 | Not Used | R | 00h | 7 bits, these bits will be used in Multi-Cycle Averaging Mode in order to allow higher averaging results. |
| 15-0 | CLOCK_COUNT5 | R | 0000h | 16 bits, CLOCK_COUNT5 measurement result |
7.6.22 TDCx_TIME6: Time 6 Register (address: 1Ah, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | TIME6: 23 bit integer value (Bit 22: MSB, Bit 0: LSB) | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 23. TDCx_TIME6 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity bit | R | 0 | Parity Bit |
| 22-0 | TIME6 | R | 00 0000h | 23 bits, TIME6 measurement result |
7.6.23 TDCx_CALIBRATION1: Calibration 1 Register (address: 1Bh, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | CALIBRATION1: 23 bit integer value (Bit 22: MSB, Bit 0: LSB) | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 24. TDCx_CALIBRATION1 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity BIt | R | 0 | Parity Bit |
| 22-0 | CALIBRATION1 | R | 00 0000h | 23 bits, Calibration 1 measurement result |
7.6.24 TDCx_CALIBRATION2: Calibration 2 Register (address: 1Ch, CSBx asserted) [reset = 00_0000h]
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Parity Bit | CALIBRATION2: 23 bit integer value (Bit 22: MSB, Bit 0: LSB) | ||||||||||||||||||||||
| R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 | R-0 |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Table 25. TDCx_CALIBRATION2 Register Field Descriptions
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | Parity BIt | R | 0 | Parity Bit |
| 22-0 | CALIBRATION2 | R | 00 0000h | 23 bits, Calibration 2 measurement result |