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ZHCSJJ3E July 2009 – April 2019 TCA9555

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

PW|24
- MPDS363A
RGE|24
- MPQF124G
DB|24
- MPDS509
RTW|24
- MPQF167C

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

RGE|24
- QFND008AA
RTW|24
- QFND062N

訂購(gòu)信息

6 Pin Configuration and Functions

DB, PW Package

24-Pin TSSOP

Top View

RTW, RGE Package

24-Pin WQFN, VQFN with Exposed Thermal Pad

Top View

The exposed thermal pad, if used, must be connected as a secondary ground or left electrically open.

Pin Functions

PIN			TYPE	DESCRIPTION
NAME	NO.
NAME	DB, PW	RTW, RGE
A0	21	18	Input	Address input 0. Connect directly to V_CC or ground
A1	2	23	Input	Address input 1. Connect directly to V_CC or ground
A2	3	24	Input	Address input 2. Connect directly to V_CC or ground
GND	12	9	GND	Ground
INT	1	22	Output	Interrupt output. Connect to V_CC through a pull-up resistor
P00	4	1	I/O	P-port I/O. Push-pull design structure. At power on, P00 is configured as an input
P01	5	2	I/O	P-port I/O. Push-pull design structure. At power on, P01 is configured as an input
P02	6	3	I/O	P-port I/O. Push-pull design structure. At power on, P02 is configured as an input
P03	7	4	I/O	P-port I/O. Push-pull design structure. At power on, P03 is configured as an input
P04	8	5	I/O	P-port I/O. Push-pull design structure. At power on, P04 is configured as an input
P05	9	6	I/O	P-port I/O. Push-pull design structure. At power on, P05 is configured as an input
P06	10	7	I/O	P-port I/O. Push-pull design structure. At power on, P06 is configured as an input
P07	11	8	I/O	P-port I/O. Push-pull design structure. At power on, P07 is configured as an input
P10	13	10	I/O	P-port I/O. Push-pull design structure. At power on, P10 is configured as an input
P11	14	11	I/O	P-port I/O. Push-pull design structure. At power on, P11 is configured as an input
P12	15	12	I/O	P-port I/O. Push-pull design structure. At power on, P12 is configured as an input
P13	16	13	I/O	P-port I/O. Push-pull design structure. At power on, P13 is configured as an input
P14	17	14	I/O	P-port I/O. Push-pull design structure. At power on, P14 is configured as an input
P15	18	15	I/O	P-port I/O. Push-pull design structure. At power on, P15 is configured as an input
P16	19	16	I/O	P-port I/O. Push-pull design structure. At power on, P16 is configured as an input
P17	20	17	I/O	P-port I/O. Push-pull design structure. At power on, P17 is configured as an input
SCL	22	19	Input	Serial clock bus. Connect to V_CC through a pull-up resistor
SDA	23	20	Input	Serial data bus. Connect to V_CC through a pull-up resistor
V_CC	24	21	Supply	Supply voltage