ZHCSEZ2D January 2014 – October 2021 TCA9539-Q1
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
封裝選項
機械數(shù)據(jù) (封裝 | 引腳)
- PW|24
散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)
訂購信息
8.6.1 Device Address
Figure 8-5 shows the address byte of the TCA9539-Q1.
Figure 8-5 TCA9539-Q1 AddressTable 8-2 shows the address reference of the TCA9539-Q1.
Table 8-2 Address Reference
| INPUTS | I2C BUS TARGET ADDRESS | |
|---|---|---|
| A1 | A0 | |
| L | L | 116 (decimal), 74 (hexadecimal) |
| L | H | 117 (decimal), 75 (hexadecimal) |
| H | L | 118 (decimal), 76 (hexadecimal) |
| H | H | 119 (decimal), 77 (hexadecimal) |
The last bit of the target address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation.