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SLLS362G SEPTEMBER 1999 – January 2016 SN65LVDS387 , SN65LVDS389 , SN65LVDS391 , SN75LVDS387 , SN75LVDS389 , SN75LVDS391

PRODUCTION DATA.

封裝選項(xiàng)

請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機(jī)械數(shù)據(jù) (封裝 | 引腳)

PW|16
D|16

散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

8 Specifications

8.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Supply voltage range, V_CC⁽²⁾		–0.5	4	V
Input voltage range	Inputs	–0.5	6	V
Input voltage range	Y or Z	–0.5	4	V
Continuous power dissipation		See Thermal Information
Lead temperature 1.6 mm (1/16 in) from case for 10 seconds			260	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground pin.

8.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	SN65' (Y, Z, and GND)	Class 3, A	±15000	V
		SN65' (Y, Z, and GND)	Class 3, B	±400	V
		SN75' (Y, Z, and GND)	Class 3, A	±4000	V
		SN75' (Y, Z, and GND)	Class 3, B	±400	V
	Lead temperature 1.6 mm (1/16 in) from case for 10 seconds			260	°C

8.3 Recommended Operating Conditions

			MIN	NOM	MAX	UNIT
V_CC	Supply voltage		3	3.3	3.6	V
V_IH	High-level input voltage		2			V
V_IL	Low-level input voltage				0.8	V
T_A	Operating free-air temperature	SN75'	0		70	°C
T_A	Operating free-air temperature	SN65'	–40		85	°C

8.4 Thermal Information

THERMAL METRIC⁽¹⁾	SN65LVDS387 SN75LVDS389	SN75LVDS387 SN65LVDS391	SN65LVDS389 SN75LVDS391		UNIT
	DGG	DBT	D	PW
	64 PINS	38 PINS	16 PINS	16 PINS
Derating Factor Above T_A = 25°C⁽²⁾	16.7	8.5	7.6	6.2	mW/°C
Power Rating: T_A≤ 25°C	2094	1071	950	774	mW
Power Rating: T_A = 70°C	1342	688	608	496
Power Rating: T_A = 85°C	1089	556	494	402

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.

8.5 Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP⁽¹⁾	MAX	UNIT
\|V_OD\|	Differential output voltage magnitude	R_L = 100 Ω, See Figure 9 and Figure 10		247	340	454	mV
Δ\|V_OD\|	Change in differential output voltage magnitude between logic states	R_L = 100 Ω, See Figure 9 and Figure 10		–50		50	mV
V_OC(SS)	Steady-state common-mode output voltage	See Figure 11		1.125		1.375	V
ΔV_OC(SS)	Change in steady-state common-mode output voltage between logic states			–50		50	mV
V_OC(PP)	Peak-to-peak common-mode output voltage				50	150	mV
I_CC	Supply current	'LVDS387	Enabled, R_L = 100 Ω, V_IN = 0.8 V or 2 V		85	95	mA
		'LVDS389			50	70
		'LVDS391			20	26
		'LVDS387	Disabled, V_IN = 0 V or V_CC		0.5	1.5
		'LVDS389			0.5	1.5
		'LVDS391			0.5	1.3
I_IH	High-level input current	V_IH = 2 V			3	20	µA
I_IL	Low-level input current	V_IL = 0.8 V			2	10	µA
I_OS	Short-circuit output current	V_OY or V_OZ = 0 V				±24	mA
I_OS	Short-circuit output current	V_OD = 0 V				±12	mA
I_OZ	High-impedance output current	V_O = 0 V or V_CC				±1	µA
I_O(OFF)	Power-off output current	V_CC = 1.5 V, V_O = 2.4 V				±1	µA
C_IN	Input capacitance	V_I = 0.4sin(4E6πt) + 0.5 V			5		pF
C_O	Output capacitance	V_I = 0.4sin(4E6πt) + 0.5 V, Disabled			9.4		pF

(1) All typical values are at 25°C and with a 3.3-V supply.

8.6 Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
t_PLH	Propagation delay time, low-to-high-level output	R_L = 100 Ω, C_L = 10 pF, See Figure 12	0.9	1.7	2.9	ns
t_PHL	Propagation delay time, high-to-low-level output		0.9	1.6	2.9	ns
t_r	Differential output signal rise time		0.4	0.8	1	ns
t_f	Differential output signal fall time		0.4	0.8	1	ns
t_sk(p)	Pulse skew (\|t_PHL – t_PLH\|)			150	500	ps
t_sk(o)	Output skew⁽²⁾			80	150	ps
t_sk(pp)	Part-to-part skew⁽³⁾				1.5	ns
t_PZH	Propagation delay time, high-impedance-to-high-level output	See Figure 13		6.4	15	ns
t_PZL	Propagation delay time, high-impedance-to-low-level output			5.9	15	ns
t_PHZ	Propagation delay time, high-level-to-high-impedance output			3.5	15	ns
t_PLZ	Propagation delay time, low-level-to-high-impedance output			4.5	15	ns

(1) All typical values are at 25°C and with a 3.3-V supply.

(2) t_sk(o) is the magnitude of the time difference between the t_PLH or t_PHL of all drivers of a single device with all of their inputs connected together.

(3) t_sk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.