ZHCSWR7I June 1998 – July 2024 SN74AHCT367
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
The SN74AHCT367 device is designed specifically to improve both the performance and density of
3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device is organized as a dual 4-line and 2-line buffer/driver with active-low output-enable (1
OE and 2
OE) inputs. When
OE is low, the device passes noninverted data from the A inputs to the Y outputs. When
OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.