ZHCSSV0D November 1995 – February 2024 SN74ACT564
PRODUCTION DATA
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Figure 3-1 SN74ACT564 DB, DW, N, NS,
or PW Package (Top View)| PIN | TYPE | Description | ||
|---|---|---|---|---|
| NO. | NAME | |||
| 1 | OE | I | Clear all channels, active low | |
| 2 | 1D | I | Channel 1, D input | |
| 3 | 2D | I | Channel 2, D input | |
| 4 | 3D | I | Channel 3, D input | |
| 5 | 4D | I | Channel 4, D input | |
| 6 | 5D | I | Channel 5, D input | |
| 7 | 6D | I | Channel 6, D input | |
| 8 | 7D | I | Channel 7, D input | |
| 9 | 8D | I | Channel 8, D input | |
| 10 | GND | — | Ground | |
| 11 | CLK | I | Clock Pin | |
| 12 | 8Q | O | Channel 8, Q output | |
| 13 | 7Q | O | Channel 7, Q output | |
| 14 | 6Q | O | Channel 6, Q output | |
| 15 | 5Q | O | Channel 5, Q output | |
| 16 | 4Q | O | Channel 4, Q output | |
| 17 | 3Q | O | Channel 3, Q output | |
| 18 | 2Q | O | Channel 2, Q output | |
| 19 | 1Q | O | Channel 1, Q output | |
| 20 | VCC | — | Power Pin | |