ZHCSJD7C April 2002 – February 2019 SN65LVDT14 , SN65LVDT41
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| 1D(1) | 1 | I | LVTTL Driver Input Pin |
| 2D(1) | 3 | ||
| 3D(1) | 5 | ||
| 4D(1) | 7 | ||
| 1Y(1) | 20 | O | Noninverting LVDS Driver Output Pin |
| 2Y(1) | 18 | ||
| 3Y(1) | 16 | ||
| 4Y(1) | 14 | ||
| 1Z(1) | 19 | O | Inverting LVDS Driver Output Pin |
| 2Z(1) | 17 | ||
| 3Z(1) | 15 | ||
| 4Z(1) | 13 | ||
| 5R | 9 | O | LVTTL Receiver Output Pin |
| 5A | 12 | I | Noninverting LVDS Receiver Input Pin |
| 5B | 11 | I | Inverting LVDS Receiver Input Pin |
| VCC | 4, 8 | I | Power Supply Pin, +3.3 V ± 0.3 V |
| GND | 2, 6, 10 | I | Ground Pin |
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| 1A(1) | 1 | I | Noninverting LVDS Receiver Input Pin |
| 2A(1) | 3 | ||
| 3A(1) | 5 | ||
| 4A(1) | 7 | ||
| 1B(1) | 2 | I | Inverting LVDS Receiver Input Pin |
| 2B(1) | 4 | ||
| 3B(1) | 6 | ||
| 4B(1) | 8 | ||
| 1R(1) | 20 | O | LVTTL Receiver Output Pin |
| 2R(1) | 18 | ||
| 3R(1) | 16 | ||
| 4R(1) | 14 | ||
| 5Y | 9 | I | Noninverting LVDS Driver Output Pin |
| 5Z | 10 | I | Inverting LVDS Driver Output Pin |
| 5D | 12 | O | LVTTL Driver Input Pin |
| GND | 11, 15, 19 | I | Ground Pin |
| VCC | 13, 17 | I | Power Supply Pin, +3.3 V ± 0.3 V |