ZHCSJD7C April 2002 – February 2019 SN65LVDT14 , SN65LVDT41
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
Table 2 shows how the LVDS receiver differential input to single-ended output relationship is defined for SN65LVDTxx. The SN65LVDTxx receiver is capable of detecting signals as low as 100 mV over a ±1-V common-mode range centered around 1.2 V.
| INPUTS | OUTPUT | |
|---|---|---|
| VID = VA – VB | R | |
| VID ≥ 100 mV | H | |
| –100 mV < VID < 100 mV | ? | |
| VID ≤ –100 mV | L | |
| Open | H | |
Table 3 shows how the LVDS driver single-ended input to differential output relationship is defined for SN65LVDTxx.
| INPUT | OUTPUTS | |
|---|---|---|
| D | Y | Z |
| H | H | L |
| L | L | H |
| Open | L | H |