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SLAS638A January 2009 – October 2015 SN65HVS885

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

PWP|28
- MPDS373B

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

PWP|28
- PPTD031AA

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
V_CC	Device power input	V_CC	–0.5	6	V
V_IPx	Field digital inputs	IPx	–0.3	36	V
V_ID	Voltage at any logic input	DB0, DB1, CLK, SIP, CE, LD	–0.5	6	V
I_O	Output current	HOT, SOP	–8	8	mA
P_TOT	Continuous total power dissipation		See Thermal Information
T_J	Junction temperature			170	°C
T_stg	Storage temperature			150	°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All pins	±4000	V
		Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	IPx	±15000
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±1000
		Machine model (MM)⁽³⁾		±100

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) JEDEC Standard 22, Method A115-A

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
V_CC	Device supply voltage	4.5	5	5.5	V
V_IPL	Field input low-state input voltage	0		4	V
V_IPH	Field input high-state input voltage	5.5		34	V
V_IL	Logic low-state input voltage	0		0.8	V
V_IH	Logic high-state input voltage	2.0		5.5	V
R_LIM	Current limiter resistor	17	25	500	kΩ
f_IP ⁽¹⁾	Input data rate	0		1	Mbps
T_A	Device	–40		125	°C
T_J	Junction Temperature			150	°C

(1) Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = GND), and R_IN = 0 Ω

6.4 Thermal Information

THERMAL METRIC⁽¹⁾			SN65HVS885	UNIT
			PWP (HTSSOP)
			28 PINS
R_θJA	Junction-to-ambient thermal resistance	High-K thermal resistance	35	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance		4.27	°C/W
R_θJB	Junction-to-board thermal resistance		15	°C/W
ψ_JT	Junction-to-top characterization parameter		0.6	°C/W
ψ_JB	Junction-to-board characterization parameter		15.9	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance		2.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over full-range of recommended operating conditions (unless otherwise noted) all voltages measured against device ground, see Figure 9

PARAMETER		TERMINAL	TEST CONDITIONS		MIN	TYP	MAX	UNIT
FIELD INPUTS
V_TH–(IP)	Low-level device input threshold voltage	IP0–IP7	R_LIM = 25 kΩ		4	4.3		V
V_TH+(IP)	High-level device input threshold voltage					5.2	5.5	V
V_HYS(IP)	Device input hysteresis					0.9		V
V_TH–(IN)	Low-level field input threshold voltage	Measured at field side of R_IN	4.5 V < V_CC < 5.5 V, R_IN = 1.2 kΩ ± 5%, R_LIM = 25 kΩ, T_A ≤ 125°C		6	8.4		V
V_TH+(IN)	High-level field input threshold voltage					9.4	10	V
V_HYS(IN)	Field input hysteresis					1		V
R_IP	Input resistance	IP0–IP7	3 V < V_IPx < 6 V, R_LIM = 25 kΩ		0.2	0.63	1.1	kΩ
I_IP-LIM	Input current limit	IP0–IP7	R_LIM = 25 kΩ		3.15	3.6	4	mA
t_DB	Debounce times of input channels	IP0–IP7	DB0 = open, DB1 = GND			0		ms
			DB0 = GND, DB1 = open			1
			DB0 = DB1 = open			3
I_RE-on	RE on-state current	RE0–RE7	R_LIM = 25 kΩ, RE_X = GND		2.8	3.15	3.5	mA
DEVICE SUPPLY
I_CC(VCC)	Supply current	V_CC	IP0 to IP7 = 24V, RE_X = GND, All logic inputs open			6.5	10	mA
LOGIC INPUTS AND OUTPUTS
V_OL	Logic low-level output voltage	SOP, HOT	I_OL = 20 μA				0.4	V
V_OH	Logic high-level output voltage	SOP, HOT	I_OH = –20 μA		4			V
I_IL	Logic input leakage current	DB0, DB1, SIP, LD, CE, CLK			–50		50	μA
T_OVER	Over-temperature indication					150		°C
T_SHDN	Shutdown temperature					170		°C
POWER DISSIPATION
P_D	Power Dissipation		V_CC = 5 V, R_IN = 0Ω, R_LIM = 25 kΩ, RE0 – RE7 = GND, f_CLK = 100 MHz	IP0-IP7 = 34 V		1100		mW
				IP0-IP7 = 24 V
				IP0-IP7 = 20 V
				IP0-IP7 = 12 V

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
t_W1	CLK pulse width	See Figure 6	4		ns
t_W2	LD pulse width	See Figure 4	6		ns
t_SU1	SIP to CLK setup time	See Figure 7	4		ns
t_H1	SIP to CLK hold time	See Figure 7	2		ns
t_SU2	Falling edge to rising edge (CE to CLK) setup time	See Figure 8	4		ns
t_REC	LD to CLK recovery time	See Figure 5	2		ns
f_CLK	Clock pulse frequency	See Figure 6	DC	100	MHz

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MAX	UNIT
t_PLH1, t_PHL1	CLK to SOP	C_L = 15 pF, see Figure 6	10	ns
t_PLH2, t_PHL2	LD to SOP	C_L = 15 pF, see Figure 4	14	ns
t_r, t_f	Rise and fall times	C_L = 15 pF, see Figure 6	6	ns

6.8 Typical Characteristics

Figure 1. Typical Input Characteristics

Figure 2. Typical Current Limiter Variation vs Ambient Temperature

Figure 3. Typical Limiter Threshold Voltage Variation vs Ambient Temperature