ZHCS603D November 2011 – April 2022 SN65HVDA100-Q1
PRODUCTION DATA
Figure 6-1 D Package, 8-Pin SOIC| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| EN | 2 | I | Enable input |
| GND | 5 | GND | Ground |
| INH | 8 | O | Inhibit controls external voltage regulator with inhibit input |
| LIN | 6 | I/O | LIN bus single-wire transmitter and receiver |
| NWake | 3 | I | High-voltage input for device wake up |
| RXD | 1 | O | RXD output (open-drain) interface reporting state of LIN bus voltage |
| TXD | 4 | I | TXD input interface to control state of LIN output |
| VSUP | 7 | Supply | Device supply voltage (connected to battery in series with external reverse blocking diode) |