ZHCSJ17H November 2002 – November 2018 SN65HVD233 , SN65HVD234 , SN65HVD235
PRODUCTION DATA.
請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| VIT+ | Positive-going input threshold voltage | AB at 0 V, LBK at 0 V, EN at VCC, See Table 1 | 750 | 900 | mV | |||
| VIT– | Negative-going input threshold voltage | 500 | 650 | |||||
| Vhys | Hysteresis voltage (VIT+ – VIT–) | 100 | ||||||
| VOH | High-level output voltage | IO = –4 mA, See Figure 17 | 2.4 | V | ||||
| VOL | Low-level output voltage | IO = 4 mA, See Figure 17 | 0.4 | |||||
| II | Bus input current | CANH or CANL at 12 V | Other bus pin at 0 V,
D at 3 V, AB at 0 V, LBK at 0 V, RS at 0 V, EN at VCC |
150 | 500 | μA | ||
| CANH or CANL at 12 V,
VCC at 0 V |
200 | 600 | ||||||
| CANH or CANL at –7 V | –610 | –150 | ||||||
| CANH or CANL at –7 V,
VCC at 0 V |
–450 | –130 | ||||||
| CI | Input capacitance (CANH or CANL) | Pin-to-ground, VI = 0.4 sin (4E6πt) + 0.5 V, D at 3 V,
AB at 0 V, LBK at 0 V, EN at VCC |
40 | pF | ||||
| CID | Differential input capacitance | Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5 V, D at 3 V,
AB at 0 V, LBK at 0 V, EN at VCC |
20 | |||||
| RID | Differential input resistance | D at 3 V, AB at 0 V, LBK at 0 V, EN at VCC | 40 | 100 | kΩ | |||
| RIN | Input resistance (CANH or CANL) to ground | 20 | 50 | |||||
| ICC | Supply current | Sleep | EN at 0 V, D at VCC, RS at 0 V or VCC | 0.05 | 2 | μA | ||
| Standby | RS at VCC, D at VCC, AB at 0 V, LBK at 0 V, EN at VCC | 200 | 600 | |||||
| Dominant | D at 0 V, No Load, RS at 0 V, LBK at 0 V, AB at 0 V,
EN at VCC |
6 | mA | |||||
| Recessive | D at VCC, No Load, RS at 0 V, LBK at 0 V, AB at 0 V,
EN at VCC |
6 | ||||||