8.5.1 Local I²C Interface Overview

The SN65DSI84-Q1 local I²C interface is enabled when EN is input high, access to the CSR registers is supported during ultra-low power state (ULPS). The SCL and SDA terminals are used for I²C clock and I²C data respectively. The SN65DSI84-Q1 I²C interface conforms to the two-wire serial interface defined by the I²C Bus Specification, Version 2.1 (January 2000), and supports fast mode transfers up to 400 kbps.

The device address byte is the first byte received following the START condition from the master device. The 7 bit device address for SN65DSI84-Q1 is factory preset to 010110X with the least significant bit being determined by the ADDR control input. Table 4 clarifies the SN65DSI84-Q1 target address.

The following procedure is followed to write to the SN65DSI84-Q1 I²C registers.

1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI84-Q1 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
2. The SN65DSI84-Q1 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within SN65DSI84-Q1) to be written, consisting of one byte of data, MSB-first.
4. The SN65DSI84-Q1 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I²C register.
6. The SN65DSI84-Q1 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the SN65DSI84-Q1.
8. The master terminates the write operation by generating a stop condition (P).

The following procedure is followed to read the SN65DSI84-Q1 I²C registers:

1. The master initiates a read operation by generating a start condition (S), followed by the SN65DSI84-Q1 7-bit address and a one-value “W/R” bit to indicate a read cycle.
2. The SN65DSI84-Q1 acknowledges the address cycle.
3. The SN65DSI84-Q1 transmit the contents of the memory registers MSB-first starting at register 00h. If a write to the SN65DSI84-Q1 I2C register occurred prior to the read, then the SN65DSI84-Q1 will start at the sub-address specified in the write.
4. The SN65DSI84-Q1 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the SN65DSI84-Q1 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).

The following procedure is followed for setting a starting sub-address for I²C reads:

1. The master initiates a write operation by generating a start condition (S), followed by the SN65DSI84-Q1 7-bit address and a zero-value “W/R” bit to indicate a write cycle
2. The SN65DSI84-Q1 acknowledges the address cycle.
3. The master presents the sub-address (I²C register within SN65DSI84-Q1) to be written, consisting of one byte of data, MSB-first.
4. The SN65DSI84-Q1 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).