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ZHCSAT9I september 2012 – october 2020 SN65DSI83

PRODUCTION DATA

封裝選項

機械數(shù)據 (封裝 | 引腳)

ZXH|64
- MPBGAK9A

散熱焊盤機械數(shù)據 (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
V_IL	Low-level control signal input voltage				0.3 × VCC	V
V_IH	High-level control signal input voltage		0.7 × VCC
V_OH	High-level output voltage	I_OH = –4 mA	1.25
V_OL	Low-level output voltage	I_OL = 4 mA			0.4
I_LKG	Input failsafe leakage current	V_CC = 0; V_CC(PIN) = 1.8 V			±30	μA
I_IH	High-level input current	Any input pin			±30
I_IL	Low-level input current	Any input pin			±30
I_OZ	High-impedance output current	Any output pin			±10
I_OS	Short-circuit output current	Any output driving GND short			±20	mA
I_CC	Device active current	See ⁽²⁾		77	112	mA
I_ULPS	Device standby current	All data and clock lanes are in ultra-low power state (ULPS)		7.7	10
I_RST	Shutdown current	EN = 0		0.04	0.06
R_EN	EN control input resistor			200		kΩ
MIPI DSI INTERFACE
V_IH-LP	LP receiver input high threshold	See Figure 6-2	880			mV
V_IL-LP	LP receiver input low threshold	See Figure 6-2			550
\|V_ID\|	HS differential input voltage		70		270
\|V_IDT\|	HS differential input voltage threshold				50
V_IL-ULPS	LP receiver input low threshold; ultra-low power state (ULPS)				300
V_CM-HS	HS common mode voltage; steady-state		70		330
ΔV_CM-HS	HS common mode peak-to-peak variation including symbol delta and interference				100
V_IH-HS	HS single-ended input high voltage	See Figure 6-2			460
V_IL-HS	HS single-ended input low voltage	See Figure 6-2	–40
V_TERM-EN	HS termination enable; single-ended input voltage (both Dp and Dn apply to enable)	Termination is switched simultaneous for Dn and Dp			450
R_DIFF-HS	HS mode differential input impedance		80		125	Ω
FlatLink LVDS OUTPUT
\|V_OD\|	Steady-state differential output voltage for A_Y x P/N and B_Y x P/N	CSR 0x19.3:2 = 00 100-Ω near-end termination	180	245	313	mV
		CSR 0x19.3:2 = 01 100-Ω near-end termination	215	293	372
		CSR 0x19.3:2 = 10 100-Ω near-end termination	250	341	430
		CSR 0x19.3:2 = 11 100-Ω near-end termination	290	389	488
		CSR 0x19.3:2 = 00 200-Ω near-end termination	150	204	261
		CSR 0x19.3:2 = 01 200-Ω near-end termination	200	271	346
		CSR 0x19.3:2 = 10 200-Ω near-end termination	250	337	428
		CSR 0x19.3:2 = 11 200-Ω near-end termination	300	402	511
	Steady-state differential output voltage for A_CLKP/N and B_CLKP/N	CSR 0x19.3:2 = 00 100-Ω near-end termination	140	191	244	mV
		CSR 0x19.3:2 = 01 100-Ω near-end termination	168	229	290
		CSR 0x19.3:2 = 01 100-Ω near-end termination	195	266	335
		CSR 0x19.3:2 = 11 100-Ω near-end termination	226	303	381
		CSR 0x19.3:2 = 00 200-Ω near-end termination	117	159	204
		CSR 0x19.3:2 = 01 200-Ω near-end termination	156	211	270
		CSR 0x19.3:2 = 10 200-Ω near-end termination	195	263	334
		CSR 0x19.3:2 = 11 200-Ω near-end termination	234	314	399
Δ\|V_OD\|	Change in steady-state differential output voltage between opposite binary states	RL = 100 Ω			35	mV
V_OC(SS)	Steady state common-mode output voltage ⁽³⁾	CSR 0x19.6 = 1 and CSR 0x1B.6 = 1 (see Figure 6-3)	0.8	0.9	1	V
V_OC(SS)	Steady state common-mode output voltage ⁽³⁾	CSR 0x19.6 = 0 (see Figure 6-3)	1.15	1.25	1.35	V
V_OC(PP)	Peak-to-peak common-mode output voltage	See Figure 6-3			35	mV
R_{LVDS_DIS}	Pulldown resistance for disabled LVDS outputs			1		kΩ

(1) All typical values are at V_CC = 1.8 V and T_A = 25°C.

(2) SN65DSI83: SINGLE Channel DSI to SINGLE Channel DSI, 1280 × 800

Number of LVDS lanes = 3 data lanes + 1 CLK lane
Number of DSI lanes = 4 data lanes + 1 CLK lane
LVDS CLK OUT = 83 M
DSI CLK = 500 M
RGB888, LVDS 18 bpp

Maximum values are at V_CC = 1.95 V and T_A = 85°C

(3) Tested at V_CC = 1.8 V , T_A = –40°C for MIN, T_A = 25°C for TYP, T_A = 85°C for max.