ZHCSFS0A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
Table 34 shows the SN65DSI83-Q1 desgin parameters.
| DESIGN PARAMETERS | EXAMPLE VALUE |
|---|---|
| VCC | 1.8 V (±5%) |
| Clock source (REFCLK or DSIA_CLK) | DSIA_CLK |
| REFCKL frequency | N/A |
| DSIA clock frequency | 500 MHz |
| PANEL INFORMATION | |
| Pixel clock (MHz) | 83 MHz |
| Horizontal active (pixels) | 1280 |
| Horizontal blanking (pixels) | 384 |
| Vertical active (lines) | 800 |
| Vertical blanking (lines) | 30 |
| Horizontal sync offset (pixels) | 64 |
| Horizontal sync pulse width (pixels) | 128 |
| Vertical sync offset (lines) | 3 |
| Vertical sync pulse width (lines) | 7 |
| PANEL INFORMATION (continued) | |
| Horizontal sync pulse polarity | Negative |
| Vertical sync pulse polarity | Negative |
| Color bit depth (6 bpc or 8 bpc) | 6-bit |
| Number of LVDS lanes | 1 × [3 Data Lanes + 1 Clock Lane] |
| DSI INFORMATION | |
| Number of DSI lanes | 1 × [4 Data Lanes + 1 Clock Lane] |
| DSI clock frequency(MHz) | 500 MHz |
| Dual DSI configuration(odd/even or left/right) | N/A |